Principal Firmware Engineer - Power Conversion Control

Job Overview

Proper Voltage designs and builds safety-critical battery energy storage systems. This role owns the real-time control firmware for our bidirectional DC/DC power conversion stage — the code that closes current and voltage loops on multiphase interleaved converters, arbitrates operating modes, and commands a safe state when a fault occurs.

This is not a general embedded role that happens to touch PWM. You will be fluent in both the control theory and the silicon: able to derive a plant model and a discrete-time compensator, implement it within a sub-microsecond ISR budget with correct fixed-point scaling and correct ADC-to-PWM trigger phasing, then measure the resulting loop gain on the bench and explain why it does or does not match the model.

You will own our portable, MCU-agnostic DC/DC control library and its normative specifications, and become the primary technical authority on converter control firmware within the organization.

What you'll do

• Real-time control loop implementation for four-switch buck-boost power stages and successor topologies, including multiphase interleaved operation and phase current balancing.
• The portable DC/DC control library: compensator implementations, mode arbitration, scheduler and ISR architecture, and the platform abstraction layer.
• Converter protection firmware — cycle-by-cycle current limit, overvoltage and undervoltage, thermal derating, gate-drive fault handling, and safe-state transitions.
• Control loop verification: model-to-measurement correlation, loop gain and stability margin characterization, transient response, and stability across the full operating envelope.
• Normative control specifications and the traceable verification evidence supporting UL 1973, UL 1998, and UL 9540 certification.

Responsibilities

• Derive small-signal plant models for buck, boost, and four-switch buck-boost topologies, and design discrete-time compensators (PID, type II/III, 2p2z/3p3z) to meet bandwidth, phase margin, and gain margin targets.
• Implement control loops in C to fixed cycle budgets using fixed-point or single-precision arithmetic as appropriate, with explicit saturation, anti-windup, and bumpless mode transfer.
• Architect and maintain the control ISR and scheduler — fast control task and slower supervisory task — with deterministic timing, measured jitter, and documented worst-case execution time.
• Configure and validate the PWM, ADC, comparator, and DAC trigger architecture, including sampling instant placement relative to switching noise, trigger-to-response latency, dead-time, and hardware-independent cycle-by-cycle protection paths.
• Implement operating mode arbitration: constant current, constant voltage, constant power, current limit, soft-start, buck-to-boost transition, phase shedding, and charge/discharge direction reversal.