Principal/Lead Design Verification Engineer - UVM/SoC

Principal / Lead Design Verification EngineerAbout the Role :

We are looking for a highly experienced Principal / Lead Design Verification Engineer to provide technical leadership for complex semiconductor, IP, subsystem, and SoC verification programs.

The role involves defining verification architecture and strategy, driving execution across teams, solving complex verification challenges, and establishing scalable verification methodologies.

Key Responsibilities :

• Define and own the overall verification strategy, architecture, methodology, and execution plan for complex IP/SoC programs.

• Lead verification teams through planning, implementation, regression, coverage closure, and final sign-off.

• Architect scalable and reusable SystemVerilog/UVM-based verification environments.

• Define verification plans, test strategies, coverage metrics, quality criteria, and sign-off methodologies.

• Drive verification of AMBA protocols, ARM CPU architectures, and complex SoC interconnects.

• Provide technical leadership for PCI Express and/or Ethernet verification.

• Establish methodologies for constrained-random verification, assertions, functional coverage, and coverage-driven verification.

• Lead complex debugging and root-cause analysis across RTL, verification environments, interfaces, and system-level interactions.

• Identify verification risks, gaps, bottlenecks, and opportunities for automation.

• Drive development of verification automation using Python, Perl, Shell, Makefile, and related scripting technologies.

• Review and guide verification architecture, test plans, environments, and critical verification components.

• Collaborate with architecture, RTL design, firmware, validation, and system engineering teams.

• Mentor senior engineers and technical leads and establish engineering best practices.

• Drive technical reviews, verification sign-offs, quality improvements, and continuous methodology enhancements.

• Contribute to project planning, technical estimation, resource allocation, and delivery commitments.

Required Skills :

• 15 - 18 years of strong experience in Design Verification / SoC Verification.

• Expert-level knowledge of SystemVerilog and UVM.

• Proven experience architecting complex functional verification environments.

• Deep expertise in AMBA protocols and ARM CPU architecture.

• Strong experience with PCI Express and/or Ethernet protocols.

• Extensive experience with constrained-random verification, assertions, functional coverage, coverage closure, and regression methodologies.

• Strong expertise in verification debugging and root-cause analysis.

• Excellent Unix/Linux and automation skills.

• Strong proficiency in Python, Perl, Shell, and/or Makefile.

• Experience with configuration management, bug tracking, regression infrastructure, and verification dashboarding.

• Proven experience leading technical teams and mentoring senior verification engineers.

Preferred Skills :

• Experience with complex CPU, SoC, subsystem, or high-performance IP verification.

• Experience defining verification methodology and architecture across multiple projects.

• Exposure to formal verification and advanced verification techniques.

• Strong understanding of verification sign-off and quality metrics.

• Experience working with geographically distributed engineering teams.

• Excellent technical communication, stakeholder management, and problem-solving skills.

What You Will Bring :

• Deep technical expertise in semiconductor design verification.

• Ability to solve complex verification and debugging challenges.

• Strong ownership of verification quality and project outcomes.

• Ability to establish scalable verification methodologies and mentor technical teams.

• A collaborative approach to working with architecture, design, firmware, and validation teams.