Principal Physical Design Engineer
- Compensation
- Not disclosed
- Location
- USA-CA San Jose Innovation Drive
- Work setup
- Not specified
- Seniority
- Principal
- Employment
- Full time
- Experience
- 12+ years
- Category
- Hardware
- Posted
Skills
Must have
- Education: B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
- Experience: 12+ years of hands-on physical design experience successfully taping out complex high-frequency, ultra-large-scale networking or AI ASICs.
- Deep Sub-Micron Expertise: Direct experience executing tapeouts in TSMC advanced nodes (N7, N5, N3) or equivalent foundry processes.
- EDA Tool Mastery: High proficiency in major physical design tool flows: P&R: Cadence Innovus Timing/STA: Synopsys PrimeTime or Cadence Tempus Extraction & IR/EM: StarRC / QRC, RedHawk DRC/LVS: Siemens
- Automation Skills: Advanced TCL, Python, and Unix shell scripting for flow automation and database manipulation.
- Communication: Excellent technical leadership, problem-solving, and cross-functional communication skills.
Nice to have
- Strong background in high-speed clock network implementation (H-tree, mesh, low-power CTS).
- Experience with power-aware implementation flows (UPF/CPF, multi-voltage domains, clock/power gating).
Full description
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Job Description:
Principal Physical Design Engineer — ASIC Products Division (APD)Location: San Jose, CA
Position Type: Full-Time
Who We Are — Physical Design Team in APD
Broadcom’s ASIC Products Division (APD) is the global leader in custom high-performance silicon solutions. We partner with the world’s most innovative technology companies—spanning hyper-scale cloud providers, AI pioneers, and tier-1 networking infrastructure leaders—to co-design and manufacture complex, custom ASICs that power the modern digital backbone.
The Physical Design team within APD is the world-class execution engine behind the industry's most advanced custom silicon. We push the limits of silicon technology by combining deep architectural expertise, advanced IP, cutting-edge physical design methodologies in 3nm/2nm nodes, and advanced 2.5D/3D chiplet integration to solve the most demanding compute and bandwidth challenges.We transform ultra-complex architectures into fully realized, high-yielding, first-pass silicon success.
What Defines Our Physical Design Team
- Pioneering First-Pass Silicon in 3nm/2nm: Our team consistently pushes the boundary of physics, taking the largest and most complex die sizes from floorplan to tapeout on leading-edge foundry nodes (N7, N5, N3, and N2).
- Record-Breaking Scale & Complexity: We regularly execute full-chip physical implementation for ultra-large-scale ASICs exceeding tens of billions of transistors, multi-gigahertz clock frequencies, and dense multi-die 2.5D/3D integration (CoWoS, HBM3/4, chiplet architectures).
- Methodology & Flow Leadership: We develop and maintain cutting-edge in-house (AI Driven) automation and methodology across different EDA tools, setting the benchmark for signoff quality and turn-around-time (TAT).
About the Role
Broadcom’s ASIC Products Division (APD) is looking for a Principal Physical Design Engineer to lead physical design implementation tasks for next-generation high-performance networking, AI/ML accelerators, and custom cloud ASICs. In this role, you will drive complex block-level floorplanning, synthesis, Place and Route (P&R), clock tree synthesis (CTS), timing closure, and signoff across cutting-edge deep sub-micron nodes (N5/N3/N2/A14).
Key Responsibilities
- Full-Flow Implementation: Lead block-level and top-level implementation from floorplanning to GDSII stream-out using Cadence Innovus
- Advanced Node Execution: Drive floorplanning, placement, CTS, routing, and timing/power optimization on advanced technology nodes (5nm, 3nm, 2nm) using multi-patterning and complex metal stacks.