Principal Physical Design Engineer - Embedded System

Job Title : Principal Engineer, Physical Design

Job Location : Bangalore, India (This position requires a full-time, on-site presence in our Bangalore, India Office).

Role & Responsibilities :

• SoC/Full-chip integration & P&R Flow Development.

• Establishes the integration plans for die with optimization for package and board constraints.

• Bump planning, Die file generation, closing loop with package team on signal and power bump placement restrictions.

• Create physical database for the IP or SoC. Collaborate with architects to optimize the placement of IPs for latency as well as die area/aspect-ratio.

• Collaborate with the design teams on clocking and dataflow to deliver the physical block level floorplans for APR.

• Derive specifications and collaterals for the IP blocks to execute the floorplan and automatic place and route (APR) at subsequent hierarchies.

• Coordinate with power delivery team on trade-offs for metal allocation for signal and power.

• Have excellent understanding on, die-per-reticle/good-die-per-wafer maximization, and right technology selection on metal layers usage maximization.

• Performs integration of all dies in a package and completes the relevant checks before tape-out.

• Supervise/lead/mentor junior team members.

Minimum Requirements :

• BE/BTech or ME/MTECH with at least 15+ years of experience on high complexity SoC designs. At least one SoC in 7nm or lower.

• Demonstrating knowledge and implementation strategies to create an IO ring in accordance with design specifications.

• Possessing deep knowledge of ESD, latch-up, and other foundry requirements, as well as placement strategies.

• Having hierarchical design implementation knowledge, including partitions/HMs/tiles push down to each core/tile.

• Understanding feed-through planning and implementation.

• PG creation and push-down methodologies.

• Understanding Analog components and their placement requirements according to design specifications.

• Demonstrating RDL knowledge and working with packaging for SoC floorplan design.

• Conducting PV clean-up on floorplan and ensuring self-derivation in all sign-offs, including Physical Verification, ESD, foundry/Analog requirements.

• Working knowledge of PnR implementation, physical verification, and STA.

• SoC RTL to GDSII implementation, with top level clocking strategizing and implementation.

• P&R flow owner which includes but not limited to scripting, flow deployment for SoC & Blocks.

Expertise that is a plus :

• In-depth knowledge of Physical Verification tools like in ICC2, Synopsys ICV, ICWBEV.

• Knowledge of Package PV checks, IO/Bump PV cleanup, PV rules viz. Antenna, Density, DFM, DFY, DPT at lower technology nodes 7nm or less.

• Led PV activities on SoC designs with expertise in DRC, LVS, DFM, HV checks and cleanup.

• Expertise in running PV checks on Flat/Hierarchical SoC designs with multiple power domains.