Principal, SMTS, DRAM Systems Architect

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

We are seeking an experience high-speed high-speed IO/Clocking Design Engineering at a Principal/Sr Member of Technical Staff (SMTS) level to join our DRAM IP Design team and contribute to the development of critical high-speed IP circuits used across Micron’s DRAM memory products. In this role, you will be responsible for the architecture, design, development, optimization, verification, and technical support of these high-speed IPs. You will focus on equalization and bandwidth extension to push the limits of circuit and process performance, analyze IO impairments as well as clock jitter and duty cycle distortion, and assess their impact on DRAM system timing. You will also develop core strategy and implement effective engineering solutions to address these challenges.

Relocation to Micron headquarter in Boise, Idaho is required for this position.

Responsibilities:

• Define, innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products.

• Apply robust high-speed circuit design techniques and enhance critical performance evaluation, including timing and jitter sensitivity, of the IO data path and clock path at circuit and full-chip level.

• Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics and their impact to product specifications at full-chip and system level.

• Work with Product Engineering and SI team to compare silicon performance with simulation results and support correlation activities.

• Collaborate with process integration and transistor modeling teams on Micron's next groundbreaking process node.

Minimum Qualifications:

• Minimum MSEE + 10 years or BSEE + 12 years of industry experience with strong background in designing high-speed IO interface, timing and clocking circuits with proven silicon successes.

• Ability to supervise layout work and understand good layout practices for high-speed circuits to minimize parasitic impacts.

• Strong communication skills with the ability to convey sophisticated technical concepts to other design peers both verbally and written.

• Mental agility and ability to multi-task is a must for this position as we work with all product types (commodity, mobile, graphics) and product teams in parallel with silicon validation efforts.

• Demonstrated ability in mentoring and coaching engineers early in their careers.