Principal Software Engineer - Compiler Development
Architect and optimize the next-generation SystemVerilog compiler for Xcelium, enabling faster verification of billion-gate AI and hyperscale chip designs using C++ and compiler theory.
- Compensation
- $117.6K–$218.4K / yr
- Location
- Burlington, MA
- Work setup
- Not specified
- Seniority
- Principal
- Employment
- Not specified
- Experience
- 5+ years
- Category
- Software engineering
- Posted
Skills
Must have
- BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
- 5+ years in Compiler Development, EDA, or High-Performance Computing.
- Expert-level C++ (modern standards) and a deep understanding of SystemVerilog or Verilog.
- Proven track record in compiler theory (lexing, parsing, semantic analysis, code generation).
- Experience with multi-threading, memory management, and cache-locality optimizations.
- An inventive spirit with the desire to challenge the status quo of traditional EDA tools.
Nice to have
- Knowledge of LLVM or similar compiler frameworks.
- Experience with Python for internal tooling and test automation.
- Familiarity with hardware verification environments (UVM).
Full description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description
Cadence Design Systems is a leading provider of the software, hardware, and intellectual property required to design complex integrated circuits and electronic systems. By offering Electronic Design Automation (EDA) tools, they enable engineers to simulate, verify, and optimize chip designs for various high-growth industries, including automotive, 5G, and hyperscale computing. Beyond software, Cadence provides specialized hardware for emulation and prototyping, alongside a strategy focused on Intelligent System Design that integrates AI and multiphysics analysis to streamline the development of modern electronics.
The Xcelium compiler and build performance team develops the compiler and code generator for Xcelium logic simulator. We are developing the next generation compiler capable of verifying highly complex chip designs
Join the team behind Xcelium, the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the SystemVerilog compiler to meet the staggering complexity of future AI and hyperscale chip designs.
We are looking for dynamic engineers who thrive on "impossible" scaling challenges and want to invent the algorithms that will power tomorrow’s silicon.
Key Responsibilities
- Language Evolution: Design and implement advanced SystemVerilog language extensions.
- Compiler Architecture: Develop and optimize high-performance front-end and code generation compiler components, focusing on intermediate representations (IR) that scale to multi-billion gate designs.
- Performance Engineering: Conduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint.
- Design Scalability: Architect compiler and simulator specifically tuned for complex AI designs, ensuring the engine can handle the massive replicated and parallel structures inherent in next-gen neural processing units (NPUs).
- Innovation & Research: Explore and prototype "blue-sky" features, LLM enhanced Compilation, parallel compilation, distributed compilation.
Qualifications
- BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience