RTL Design Engineer – Interconnect & Network Datapath
- Compensation
- $225K–$445K / yr
- Location
- San Francisco
- Work setup
- Hybrid
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- Not specified
- Category
- Hardware
- Posted
Skills
Nice to have
- Experience designing packet-switched interconnect or networking datapaths for AI accelerators, GPUs, CPUs, HPC systems, NICs/SmartNICs, switch ASICs, or large-scale datacenter silicon.
- Experience addressing virtualization, isolation, RAS, telemetry, security, or memory-consistency requirements within complex networking or interconnect subsystems.
- Experience with network or NoC performance modeling, traffic simulation, emulation, FPGA prototyping, or post-silicon traffic and performance analysis.
- Experience leading architecture or RTL delivery for first-generation networking or interconnect IP in rapidly evolving silicon programs.
Full description
About the Team
OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.
About the Role
We are looking for a highly experienced, hands-on RTL engineer with deep packet-networking and interconnect expertise to own critical on- and off-chip communication components for our custom AI accelerator platform.
You will drive the microarchitecture and RTL implementation of scalable on-chip fabrics connecting high-bandwidth compute, memory, and I/O subsystems, as well as purpose-built off-chip interfaces and protocols that enable custom computing at scale. The ideal candidate has recently owned production RTL for networking or packet-switched datapaths such as Ethernet switches, NICs, SmartNICs, network accelerators, RDMA/RoCE systems, NoCs, or custom scale-up/scale-out fabrics.
This is a senior engineering role with broad technical ownership and substantial direct RTL work. You will drive designs from requirements and performance analysis through microarchitecture, SystemVerilog implementation, verification closure, physical design convergence, silicon bring-up, and production readiness. You will also plan and oversee the work of junior engineers and help develop productive engineering relationships with external partners.
In this role, you will:
- Own the microarchitecture, RTL design, and delivery of major packet-based interconnect and networking components, including NoC fabrics, switches, routers, bridges, protocol adapters, arbiters, queues, schedulers, buffers, and traffic-management logic.
- Design mechanisms for routing, arbitration, ordering, flow control, congestion management, quality of service, packet scheduling, buffering, and performance monitoring.
- Develop on-chip and off-chip interfaces, protocol bridges, and custom networking protocols or protocol extensions for scale-up and scale-out systems.
- Perform substantial direct microarchitecture, SystemVerilog coding, simulation, and debug work.
- Collaborate with architecture and performance teams to analyze traffic patterns, identify bottlenecks, and optimize latency, bandwidth, fairness, and utilization under realistic workloads.
- Work with verification teams to develop coverage plans, assertions, stress scenarios, and debug strategies for highly concurrent packet and fabric behavior.
- Partner with physical design teams on floorplan-aware design, pipeline strategy, timing closure, power, area, and physical congestion.