RTL Design & IP Release Engineer
Supports semiconductor Foundation IP development at Capgemini Engineering in Brasov, Romania: implementing and validating RTL Verilog design changes, running QA checks, and managing ClearCase-based IP release flows with Python automation. Core tech: Verilog/SystemVerilog, ASIC design, CDC/Lint, AMBA protocols, Linux.
- Compensation
- Not disclosed
- Location
- Not listed
- Work setup
- Not specified
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- 1+ years
- Category
- Design
- Posted
Skills
Must have
- 1-4 years of experience
- RTL integration, ASIC design
- CDC, Lint
- Verilog/SystemVerilog
- AMBA protocols
- Scripting
- DesignSync
- Linux
- Verilog
- ClearCase-based release process management
Nice to have
- IP release flow
- Physical Verification
- Python
Full description
About Capgemini:
At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.
Job Description:
1-4 years of experience
Support Foundation IP development and release activities through RTL Verilog updates, quality assurance, and release management. Responsibilities include implementing and validating RTL design changes, managing ClearCase-based release processes, performing QA checks for Foundation IP deliverables, and enhancing release workflows through Python scripting and automation.
The role requires close collaboration across multiple global sites and cross-functional teams, with a strong focus on daily communication, coordination, and proactive issue resolution to ensure project milestones and release deadlines are met. The successful candidate will work with design, verification, integration, and program teams to deliver high-quality IP releases, improve process efficiency, and maintain configuration management and release documentation.
Must Have:
- RTL integration, ASIC design 2. CDC, Lint 3. Verilog/system verilog 4. AMBA protocols 5. scripting
- DesignSync
- Linux
- Scripting
- Verilog
Nice To Have:
- IP release flow
- Physical Verification
- Python
What Will You Love About Working Here:
- Collaborative and Inclusive Culture: You’ll work alongside passionate engineers striving to provide the best service to our clients and communities with shared interests and identities, in a dynamic environment involving teams spread across different global locations.
- Flexibility and Growth: Enjoy flexible working hours and access to a wide range of professional development opportunities, including training programs, learning platforms and certifications. Whether you're diving into Generative AI, data science, or sustainability, our digital campus supports your learning journey every step of the way;
- Comprehensive Benefits: Benefit from an attractive package including medical services, eye glasses coverage, Benefit online, meal tickets, Employee Assistance Program (covering financial, legal, and emotional matters), and the Employee Share Option Plan.