RTL Design Manager
Leads a team designing high-performance, low-power System-on-Chip (SOC) components using Verilog/System Verilog, UPF, and industry-standard EDA tools.
- Compensation
- Not disclosed
- Location
- IN,Hyderabad-Sattva
- Work setup
- Not specified
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- 12+ years
- Category
- Design
- Posted
Skills
Must have
- Digital design and RTL design in Verilog/System Verilog
- SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
- Specifying timing constraints with multiple clock domains and modes
- Designing with multiple power domains and islands using UPF
- TCL, Python, Perl scripting
- Version control systems such as Perforce, IC Manage or Git
- Fluent in Linux and Windows environments
- Solid understanding of DFT technologies and execution of DFT flows
- Basic experience with Synopsys Design Compiler and Primetime
- Bachelors or Masters degree in Electrical Engineering with 12+ years of experience
- Strong verbal and written communication skills
- Ability to organize and present complex technical information
- Project planning and management of execution from Microarchitecture to Timing Closure
- Team building experience
Full description
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.
AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.
THE ROLE:
- AMD is seeking a capable and motivated SOC Design Manager to be part of Front End SOC Design Team of next generation Adaptable Compute Acceleration Platform devices
- You will manage team working on design and implementation of high-performance, low-power SOCs and SOC Chiplets targeting a wide range of applications as well as customer specific products
- This high visibility and critical role will require technical leadership in developing microarchitecture, implementing functions in RTL, integrating IP from internal and external sources, ensuring quality and getting design ready for synthesis.
- You will also contribute to definition/evolution of IP/SOC Design methodologies and processes for future projects
THE PERSON:
- Successful candidate will have an SOC/ASIC Design background, team/project management experience, would have participated in several silicon design projects with increasing level of scope/responsibilities and has a history of achieving results through effective execution
KEY RESPONISIBILITES:
- Team management (hiring, coaching, reviewing and retaining engineers)
- Project Planning
- Tracking Project Execution and reporting of key metrics
- Managing Design reviews around feature and quality
- Retrospectives and project wind-down
- Crossfunctional stakeholder management (marketing, architecture, verification, physical design, chip integration, applications, methodology experts, management)
- Participate in tapeout checklists and reviews
- Improve processes for team through AI adoption and traditional automation
REQUIRED EXPERIENCE:
- Engineering
- Digital design and experience with RTL design in Verilog/System Verilog
- Solid understanding of DFT technologies and some experience with execution of DFT flows
- Experience with SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
- Experience in specifying timing constraints with several clock domains and modes