RTL Designer – Physical AI Compute

Design and optimize RTL for key portions of a Physical AI SoC, develop microarchitectures, define hardware interfaces and execution flows, contribute to compute and memory subsystems, optimize performance, power, and area, and collaborate through verification and physical design.

Responsibilities

• Design, implement, and optimize RTL for key SoC components
• Develop robust and efficient microarchitectures
• Define hardware interfaces, execution flows, and memory hierarchies
• Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and power-management logic
• Optimize designs for performance, power, area, scalability, and reliability
• Analyze performance bottlenecks and propose improvements
• Participate in design reviews

Requirements

• Experience designing RTL for complex digital systems
• Strong understanding of computer architecture, microarchitecture, and digital design fundamentals
• Experience with Verilog and SystemVerilog
• Familiarity with performance, power, and area tradeoffs
• Understanding of memory systems, interconnects, caches, DMA engines, or accelerator architectures
• Experience with hardware/software co-design and system-level performance optimization
• Strong debugging and problem-solving skills

Benefits

• Performance-based incentives
• Equity participation
• Medical coverage
• Dental coverage
• Vision coverage
• Paid time off
• Flexible work arrangements