Semiconductor Principal Design Engineer, Non‑Volatile Engineering Group

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The Principal Design Engineer in Micron’s NVEG (Non‑Volatile Engineering Group) organization will own and evolve the timing-critical circuitry between the NAND array and page buffer.

This role is for a designer who is equally strong in architecture, transistor-level implementation, and physical aware timing closure – and who can lead technical direction across teams to deliver robust, scalable datapath solutions. You will drive designs that directly impact throughput, timing margin, power and yield, partnering closely with page buffer, array device, clocking, physical design, test, and product teams.

Responsibilities

• Own internal NAND datapath circuits including array redundancy circuits, wave pipeline / pulse based datapath arctitechture and data line sensing circuits. Define scalable datapath architecture supporting multi-plane and high-parallelism operation.
• Define and analyse clock/data timing schemes for long interconnects and large-array topologies. Lead timing adjustment and skew management strategy.
• Drive layout-aware circuit design with attention to: matching/symmetry for sensing paths, shielding/guarding for sensitive nodes. Parasitic-aware sizing and RC-driven timing closure. Array pitch constraints, blockages and repeatable layout templates. Partner tightly with layout to review critical routes and implement practical fixes.
• Perform SPICE/Fast-SPICE simulations across PVT, aging and variability via Monte Carlo. Define characterization structures and debug plans to correlate silicon behavior vs. simulation. Drive root-cause analysis for margin/yield issues tied to datapath timing, redundancy paths or sensing robustness.
• Lead design reviews and unblock partners with clear technical decisions. Mentor other engineers; create reusable design collateral (checklists, templates, signoff methodology). Communicate tradeoffs effectively (PPA, margin, schedule, risk) and propose mitigation plans
• Communicate with project integration and other functional teams in design on specifications of major block interfaces

Minimum Qualifications

• BS or MS in Electrical Engineering with 8+ years of relevant experience
• Experience in physical design flows and optimization
• Proven ownership of blocks from concept -> design -> layout -> signoff -> silicon correlation,
• Deep expertise in:
• CMOS analog/mixed-signal circuit design and device physics fundamentals
• High-speed datapath timing analysis (including nontraditional timing such as wave-pipelined/pulse-based)