Senior Circuit Design Engineer

Meet the Team

As part of the team behind Cisco Silicon One—the industry’s only unified silicon architecture spanning top-of-rack switches to web-scale data centers—you’ll help shape Cisco’s groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry. Our international group focuses on groundbreaking process technology to ensure the efficiency and performance of our ASIC products.

Your Impact

As an ASIC Circuit Design Engineer, you will own the end-to-end development of high-performance ASIC subsystems and reusable IP. You will contribute to achieving aggressive power, performance, area, and reliability goals by developing custom digital and analog/mixed-signal blocks. You will work closely with architecture, physical design, and silicon validation teams to ensure our IP is optimized for the next generation of networking silicon, while employing automation to drive quality and productivity across the entire product lifecycle.

Key Responsibilities

• Drive the architecture, design, and implementation of high-performance ASIC subsystems and IP from specification through silicon validation.
• Develop and productize standard-cell, custom digital, and analog/mixed-signal IP to meet strict performance and robustness requirements.
• Perform transistor-level simulation and optimization, accounting for process, voltage, temperature, and aging conditions.
• Define and implement characterization methodologies for standard-cell and mixed-signal models, including the deployment of automated EDA flows.
• Collaborate with multi-functional teams, including physical design and system architecture, to define interface requirements and implementation constraints.
• Own the physical implementation of complex custom blocks, optimizing for timing, power, signal integrity, and layout-dependent effects.
• Analyze silicon results post-bring-up to drive improvements in circuit design, characterization models, and future IP architectures.
• Drive technical reviews for schematics, layouts, and methodologies to resolve complex cross-disciplinary issues and mitigate architectural risks.
• Develop reusable infrastructure, scripts, and documentation to improve engineering productivity and design quality.
• Apply expertise in advanced process nodes, including FinFET and GAA, to push the boundaries of ASIC power-delivery and clocking solutions.

Minimum Qualifications

• Bachelor’s degree and 7 years of related experience, or Master’s degree plus 4 years of related experience, or PhD plus 1 year of related experience.
• Relevant experience should include ASIC, custom digital, standard-cell, or analog/mixed-signal circuit design and implementation.

Preferred Qualifications