Senior Design Engineer
- Compensation
- Not disclosed
- Location
- Bangalore, Karnataka, India
- Work setup
- Hybrid
- Seniority
- Senior
- Employment
- Not specified
- Experience
- 3+ years
- Category
- Engineering design
- Posted
Skills
Must have
- BSEE with 4+ years of relevant circuit design and/or standard cell characterization experience, or MSEE with 3+ years of relevant experience.
- Experience identifying, designing, optimizing, and verifying standard cells specifically targeted at improving core- and SoC-level PPA.
- Strong understanding of MOSFET electrical characteristics, transistor-level device physics, circuit behavior, PPA trade-offs, layout effects, and process variability, particularly for advanced process
- Expertise in transistor-level design and analysis of static CMOS circuits, including state-retaining elements such as latches and flip-flops.
- Extensive hands-on experience with standard cell characterization, EDA view generation, modeling, and QA/validation.
- Proficiency with industry-standard cell characterization tools and SPICE-level circuit simulators.
- Proficiency in scripting and automation using languages such as Python and/or Perl.
- Strong analytical and problem-solving skills, with the ability to investigate complex circuit and characterization issues and iteratively develop effective solutions.
- Ability to clearly communicate technical findings, conclusions, trade-offs, and recommendations.
- Demonstrated ability to collaborate effectively across engineering disciplines, manage diverse responsibilities, continuously develop technical skills, and contribute positively to a team environment.
Nice to have
- Exposure to physical design implementation flows, including place-and-route and signoff methodologies.
- Familiarity with advanced-node design considerations and their impact on standard cell architecture, characterization, and implementation.
- Experience developing automation or methodology improvements for standard cell design, characterization, or validation flows.
Full description
Our Solutions Engineering Physical IP team comprises some of the industry’s leading experts in advanced deep-submicron circuit design. This role offers an exciting opportunity to join our Custom Standard Cell Design Engineering team and contribute to innovative technologies at the most advanced process nodes.
In this position, you will develop Arm custom standard cells targeting the latest sub-3nm process technologies. Working closely with circuit and physical design engineers, you will co-optimize cell architectures and implementations to improve the power, performance, and area (PPA) of Arm cores integrated into best-in-class SoCs across infrastructure, client, automotive, and IoT market segments.
You will collaborate closely with mask design engineers to achieve optimally tuned layouts and will be responsible for standard cell characterization, modeling, EDA view generation, and validation through comprehensive QA flows using industry-standard EDA tools.
The ideal candidate brings strong expertise in transistor-level circuit design, standard cell characterization, design verification, and automation. This role is critical to delivering high-performance, low-power logic libraries for next-generation SoCs and custom digital IP.
Key Responsibilities
- Develop and optimize Arm custom standard cells for advanced sub-3nm process technology nodes.
- Perform standard cell characterization, modeling, and EDA view generation, ensuring that generated models accurately represent circuit and design intent.
- Design, analyze, and verify transistor-level circuits to meet demanding power, performance, area, and reliability requirements.
- Co-optimize circuit designs with physical design engineers to improve core- and SoC-level PPA.
- Collaborate closely with mask design engineers to optimize cell layouts for electrical performance, area, manufacturability, and design-rule compliance.
- Develop and execute robust QA and validation methodologies across standard cell library views using a variety of EDA tools.
- Identify opportunities to improve characterization methodologies, automation, tools, and development processes, and drive these improvements across project teams and related functions.
- Collaborate effectively across circuit design, physical design, mask design, methodology, and other engineering teams to deliver production-quality standard cell libraries.
- Analyze complex technical issues, develop practical solutions, and clearly communicate conclusions and recommendations to engineering stakeholders.
Required Skills and Experience
- BSEE with 4+ years of relevant circuit design and/or standard cell characterization experience, or MSEE with 3+ years of relevant experience.
- Experience identifying, designing, optimizing, and verifying standard cells specifically targeted at improving core- and SoC-level PPA.