Senior Design Verification Engineer - Bangalore
Velaura is hiring a Senior Design Verification Engineer in Bangalore to verify its next-generation Physical AI SoC — building UVM/SystemVerilog testbenches, running formal, emulation, and FPGA prototyping, performing HW/SW co-verification, and debugging issues from RTL blocks to post-silicon.
- Compensation
- Not disclosed
- Location
- Bangalore
- Work setup
- Onsite
- Seniority
- Senior
- Employment
- Not specified
- Experience
- 10+ years
- Category
- Design
- Posted
Skills
Must have
- 10+ years of experience verifying complex digital systems
- Strong analytical and problem-solving skills
- Strong understanding of computer architecture, microarchitecture, SoC architecture and digital design fundamentals
- Experience with low power methodologies and verification criteria
- Strong understanding of CDC issues, clocking and reset verification
- Experience with SystemVerilog, UVM, C/C++, assertions, coverage-driven verification
- Familiarity with formal verification techniques and tools
- Experience with emulation, FPGA prototyping, or pre-silicon validation environments
- Understanding of memory systems, interconnect fabrics, caches, DMA engines, processors, or accelerator architectures
- Experience debugging complex system-level issues
- Ability to work effectively in a collaborative, multidisciplinary engineering environment
Nice to have
- Experience with functional safety standards such as ISO 26262, IEC 61508, IEC 61511, ISO 13849
- Experience with AI, machine learning, or edge AI hardware
- Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems
- Experience verifying QoS, latency-sensitive, or real-time systems
- Experience with HW/SW co-verification and system-level validation
- Exposure to performance modeling, profiling, and workload characterization
- Experience using modern AI tools and workflows to accelerate engineering productivity
- Background in CPUs, GPUs, AI accelerators, networking silicon, storage, robotics/autonomous systems, automotive/ADAS, aerospace/defense, or functional safety
Full description
Role Overview
We are looking for talented Design Verification Engineers to help verify and deliver Velaura’s next-generation Physical AI SoC. In this role, you will work closely with architects, RTL engineers, software engineers, and system teams to verify complex hardware blocks and system-level behavior across the entire platform. You will help establish confidence in the correctness, performance, reliability, and safety of the architecture—from individual RTL blocks to complete HW/SW systems running real-world workloads. We welcome engineers at all experience levels who enjoy understanding systems, finding corner cases, and solving challenging technical problems.
Responsibilities
● Develop and execute verification strategies for key portions of the Velaura SoC.
● Build verification environments using SystemVerilog, UVM, C/C++, assertions, formal verification, emulation, and related methodologies.
● Collaborate with architects and RTL engineers to define verification plans, coverage goals, and correctness criteria.
● Verify compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other critical SoC infrastructure.
● Perform HW/SW co-verification involving firmware, drivers, runtime software, and operating system interactions.
● Verify performance, latency, bandwidth, QoS, and real-time system behavior under representative workloads.
● Develop assertions, checkers, scoreboards, and automated verification infrastructure.
● Participate in emulation, FPGA prototyping, and pre-silicon software bring-up activities.
● Drive bug investigation, root-cause analysis, and debug across hardware and software boundaries.
● Post-silicon debug and root cause analysis.
● Leverage modern engineering tools, including AI-assisted verification workflows, to improve productivity, quality, and coverage.
● Contribute to a culture of technical excellence and continuous improvement.
Required Qualifications
● 10+ Years of experience verifying complex digital systems.
● Strong analytical and problem-solving skills.
● Strong understanding of computer architecture, microarchitecture, SoC architecture and digital design fundamentals.
● Experience in understanding low power methodologies and verification criteria.
● Strong understanding of CDC issues, clocking and reset verification.
● Experience with SystemVerilog, UVM, C/C++, assertions, coverage-driven verification, and related methodologies.