Senior Design Verification Engineer

Role Overview

TylSemi Solutions Private Limited is looking for a motivated and detail-oriented Senior Design Verification Engineer to join our growing Verification team. In this role, you will contribute to the verification of cutting-edge SoCs and IPs targeting AI, HPC, and Networking applications. You will work closely with experienced verification engineers and architects to develop testbenches, create test scenarios, analyze coverage, and help ensure high-quality silicon delivery.

This is an excellent opportunity for engineers who are passionate about digital design, verification methodologies, and next-generation semiconductor technologies.

What You'll Do

• Develop and execute verification test plans for IPs, subsystems, and SoC components.
• Create and maintain SystemVerilog/UVM-based verification environments.
• Write directed and constrained-random test cases to validate design functionality.
• Develop functional coverage models and assist in coverage closure activities.
• Debug simulation failures and collaborate with design engineers to resolve issues.
• Write assertions (SVA) to improve design checking and verification quality.
• Participate in regression execution, result analysis, and reporting.
• Support IP integration and subsystem-level verification activities.
• Learn and apply industry-standard verification methodologies and best practices.
• Contribute to automation scripts for regression, reporting, and verification productivity.
• Work closely with Design, Architecture, and Software teams to understand requirements and verify functionality.

What We're Looking For

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.
• 5+ years of experience in Design Verification.
• Strong understanding of digital design fundamentals and computer architecture.
• Knowledge of:

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• Verilog/SystemVerilog
• UVM methodology
• Simulation and debugging concepts
• Functional and code coverage
• Basic scripting (Python, Perl, Shell, or TCL)

• Familiarity with verification tools from Synopsys, Cadence, or Siemens EDA.
• Understanding of common protocols such as PCIe, CXL, Ethernet, UCIe protocols, is a plus.
• Good analytical and debugging skills.
• Strong communication and teamwork abilities.

Preferred Qualifications

• Project experience in ASIC/SoC verification.
• Experience in protocols such as PCIe, CXL, Ethernet, UCIe protocols, is a plus.
• Exposure to SystemVerilog assertions (SVA).