Senior Design Verification Engineer

**Job Description :
Role & Responsibilities :**

• Develop and maintain robust UVM-based verification environments for IP and SoC designs.

• Design, implement, and execute comprehensive verification test plans and strategies.

• Verify complex digital designs using SystemVerilog, UVM, and industry-standard methodologies.

• Perform functional coverage analysis, debugging, and regression management.

• Collaborate closely with RTL designers, architects, and cross-functional engineering teams.

• Drive verification closure while ensuring quality, performance, and schedule objectives.

• Mentor junior team members.

Preferred candidate profile :

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Science, or a related discipline.

• 10+ years of hands-on experience in ASIC/SoC Design Verification.

• Strong expertise in SystemVerilog and UVM methodology.

• Good programming skills in C/C++.

• Strong understanding of digital design fundamentals and ASIC verification flows.

• Hands-on experience with one or more industry-standard protocols such as :

• PCIe (PCI Express)

• UCIe

• CXL

• RISC-V

• Experience working with commercial simulators and debugging complex verification environments.

Preferred Skills :

Experience with one or more of the following will be an added advantage :

• AXI

• AHB/APB

• USB

• Functional Coverage

• Constrained Random Verification

• Assertion-Based Verification

• IP and SoC Verification

• Regression Automation and Debugging