Senior Digital Design Engineer

【About Us】
VICI Holdings' Hardware team is seeking a Senior Digital Design Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading digital hardware development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build ultra-low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars.

【Roles/ Responsibilities】

• Micro-architecture, design and implement high-performance digital circuits optimized for low-latency application
• Develop high speed data paths, ensuring minimal logic depth and efficient pipeline
• Optimize critical paths and combinational logic to reduce propagation delays and improve throughput
• Work with Verilog/ SystemVerilog to implement RTL design
• Apply parallelism and resource sharing techniques to enhance performance and throughput
• Develop latency-aware micro-architectures for real-time processing and networking applications
• Debug, optimize and iterate on designs using FPGA platform and cycle-accurate simulation
• Work closely with digital/system verification engineers to ensure functional correctness and performance validation
• Take ownership of FPGA verification tasks to ensure design correctness and performance.
• Develop and execute verification plans for high-speed IPs such as PCIe, Ethernet, and Switches.
• Support system validation engineer to debug FPGA issue

Design Collaboration:

• Collaborate closely with Algorithm, software, design validation and application team to define micro-architecture

Performance Analysis:

• Conduct performance testing and analysis, ensuring the low-latency goals are met across various use cases.
• Capability to solve routing timing issue and analysis FPGA timing report result.

【Candidate Requirements】

• Master’s degree or above in EE, CE, or CS, plus 3–8 years of high-speed digital-design experience
• Hands-on experience in IP-level digital-circuit design or IP integration (preferred)
• Proficient in debugging and optimization with VCS and Verdi simulation tools
• Comfortable working in Linux/Unix environments
• Strong analytical and problem-solving skills with a performance-driven mindset

【Other Requirements】

• Proven ability to solve complex design challenges and deliver robust solutions
• Experience designing ultra-low-latency data paths—arithmetic units, multiplexers, FIFOs, registers—for high-performance applications (preferred)
• Familiarity with FPGA verification tools such as Quartus or Vivado (a plus)
• Knowledge of high-bandwidth memory interfaces (DDR, HBM, etc.)
• Understanding of networking protocols (Ethernet, PCIe, etc.)

【Interview Process】

• Resume Screening → HR Phone Screen → Face-to-Face Interview (with 30-60mins on-site coding test)