Senior FPGA Engineer

Why Castelion, Why Now

Castelion is moving incredibly fast to develop and deliver advanced defense systems at a time when execution matters more than ever. We believe focus, ownership, and excellence are decisive advantages - and we're building a world-class team to turn bold ideas into real capability.

This is a rare opportunity to join at an early stage, where you'll have significant ownership, collaborate with exceptional teammates, and make a direct, measurable impact on our mission and the future of the company - regardless of your function.

Senior FPGA Engineer

Castelion is seeking a Senior FPGA Engineer with strong experience in Vitis HLS and High-Level Synthesis workflows to support the development of high-performance digital systems for mission-critical hardware. This is a high-impact, full-time role focused on accelerating FPGA development by translating algorithmic and system-level requirements into efficient FPGA implementations using C/C++-based design flows.

You will work closely with our hardware, software, and systems engineering teams to implement and optimize FPGA-based processing capabilities. This role is ideal for an engineer who can ramp quickly, contribute immediately, and deliver optimized hardware implementations in a fast-moving development environment.

Responsibilities

• Develop FPGA-based implementations using Vitis HLS to generate VHDL/Verilog from C/C++ code

• Translate algorithms and system requirements into efficient hardware architectures optimized for performance and latency

• Develop and optimize high-level synthesis pipelines and dataflow architectures

• Collaborate with software, avionics, and systems engineers to integrate FPGA functionality into embedded platforms

• Perform FPGA simulation, synthesis, timing analysis, and hardware validation

• Optimize designs for throughput, determinism, and resource utilization

• Support hardware integration, board bring-up, and debugging as needed

• Contribute to verification and testing of FPGA functionality

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field

• Demonstrated experience using Vitis HLS or similar High-Level Synthesis tools

• Strong C/C++ programming experience for hardware-oriented development

• Experience generating VHDL or Verilog from HLS workflows

• Familiarity with FPGA development flows including simulation, synthesis, and timing closure

• Experience with Xilinx/AMD FPGA platforms and toolchains