Senior Hardware Recruiter
Full-cycle technical recruiter for Normal Computing's silicon organization, sourcing and closing senior hardware, ASIC, and silicon architecture engineers (often passive candidates) out of Mountain View. The role leans on semiconductor domain fluency, deep partnership with engineering hiring managers, WHO Method calibration, and Ashby ATS ownership.
- Compensation
- $165K–$195K / yr
- Location
- Mountain View
- Work setup
- Hybrid
- Seniority
- Senior
- Employment
- Not specified
- Experience
- 6+ years
- Category
- Hardware
- Posted
Skills
Must have
- 6+ years of full-cycle technical recruiting, including direct experience recruiting AI, ASIC, silicon, or semiconductor engineers (RTL, DV, physical design, architecture, or adjacent roles)
- Track record of closing senior engineers against competing offers (selling equity, risk, and conviction)
- Technical literacy across deep-tech: AI silicon and custom ASIC development; able to hold a credible intake conversation with a chip architect
- Advanced fluency in Ashby (or comparable ATS) for candidate tracking, reporting, and process automation
- Operational excellence: low ego, comfortable with ambiguity, able to move work forward at the volume of a scaling startup
Nice to have
- Exposure to AI/ML and software engineering recruiting in addition to hardware expertise
- Experience recruiting for unconventional computing or physics-based hardware architectures
- Previous experience in a high-growth venture-backed startup, semiconductor company, or research lab
Full description
Normal Computing | Build with Us
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), and London.
The Role
Recruiting silicon talent is a specialist's craft: the candidate pool is small, every strong architect and DV engineer is fielding multiple offers, and the people you're hunting can smell a recruiter who doesn't know what a tapeout is.
As a Senior Hardware Recruiter, you will work on full-cycle recruiting for Normal's silicon organization. You will partner directly with hiring managers who are themselves deep technologists, source candidates who aren't looking, and close people who have every option.
What You'll Own
- Full-Cycle Recruiting: Manage an end-to-end recruitment process for senior hardware, ASIC, and silicon architecture roles from intake through close, flexing to AI, silicon software, and other technical searches as priorities shift.
- Strategic Sourcing: Identify and engage top-tier talent in unconventional silicon architecture, design verification, and systems architecture: people who are rarely on the market and need a reason to talk.
- Engineering Partnership: Act as a strategic partner to engineering hiring managers, aligning on candidate qualifications, technical bars, and calibration as searches evolve.
- Process Discipline: Run the WHO Method for talent calibration and maintain high-efficiency interview loops, targeting 4-5 rounds maximum so great candidates don't die in process.
- ATS Ownership: Maintain impeccable data hygiene and pipeline flow in Ashby: clean stages, honest statuses, reporting the team can trust.
- Brand Ambassadorship: Represent Normal Computing at industry events like DAC, engaging specialized candidates in the rooms where they actually gather.
What Makes You a Great Fit
- 6+ years of full-cycle technical recruiting, including direct experience recruiting AI, ASIC, silicon, or semiconductor engineers: RTL, DV, physical design, architecture, or adjacent roles
- A track record of closing senior engineers against competing offers: you know how to sell equity, risk, and conviction, not just a comp number
- Technical literacy across the deep-tech landscape: AI silicon, and custom ASIC development — you can hold a credible intake conversation with a chip architect