Senior Implementation Engineer

We are seeking a highly experienced ASIC Physical Design Engineer with 12+ years of hands-on expertise in full-chip and hierarchical SoC physical design.

This role requires deep technical expertise in advanced technology nodes, strong problem-solving capability, and leadership in driving chip closure from netlist to GDSII.

Job Overview:

Responsibilities:

• Lead chip-level hierarchical floor planning and block-level integration.

• Drive partitioning strategy, partition push-down, and hierarchical design implementation.

• Own pin planning, IO planning, bump planning, and bump routing for complex SoCs.

• Define and execute power planning (ring/mesh/grid architecture, multi-domain handling).

• Perform and manage full-chip CTS and clock architecture optimization.

• Lead chip integration activities across multiple blocks and subsystems.

• Execute and sign off physical verification (DRC, LVS, ERC, ESD, antenna, etc.).

• Handle ESD planning and implementation at chip level.

• Drive full-chip closure including congestion, IR/EM, timing, and noise analysis.

• Collaborate closely with RTL, synthesis, STA, package, and backend teams.

• Support tape-out activities and resolve last-mile issues.

• Mentor junior engineers and provide technical guidance on chip-level challenges.

Required Skills and Experience :

Education:

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Microelectronics, or related field!

Mandatory Experience:

• Chip-level hierarchical floor planning

• Partitioning & partition push-down

• Pin planning & IO planning

• Bump planning & bump routing

• ESD planning

• Full-chip integration

• Physical verification (DRC/LVS/ERC/Antenna), IR DROP, SI-Noise Signoff.

• Full-chip CTS

• Power planning (multi-voltage domains, UPF awareness)

• Hands-on experience with leading EDA tools (e.g., Innovus, ICC2, Fusion Compiler, Tempus, PrimeTime, Calibre, etc.)

• Experience in advanced nodes (5nm/3nm/2nm or similar preferred)

“Nice To Have” Skills and Experience :

• Experience leading full-chip tape-outs.

• Knowledge of packaging interactions and bump/IO co-design.

• Ability to script and automate workflows using Python, TCL, or SKILL.

• Familiar with Cadence/Synopsys/Mentor tools

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