Senior Logic Design Engineer

At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You’ll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress. - Lead the microarchitecture, design and development of Instruction Fetch Unit for high-performance Processor CPU of IBM Systems. - Micro-Architect and design Instruction Fetch, Instruction Decode, Branch Predictors, Instruction Queue for a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - 8 to 15 or more years of demonstrated experience in architecting and designing Instruction Fetch, Decode and Branch Predictor unit of CPU - Hands of experience of implementing Issue Queues, Arrays, Caches, Reordering Buffer and Pipeline flush/exception handling - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL Knowledge of Out-of-Order, Memory and Execution units Knowledge of verification principles and coverage High-level knowledge of Linux operating system Knowledge of one object oriented language and scripting language Understanding of Agile development processes Experience with DevOps design methodologies and tools Advanced Static Timing: Deep understanding of static timing and its application in chip logic development can be advantageous in driving business results. Front-end Processing Expertise: Familiarity with front-end processing and its role in chip logic development can be valuable in shaping the future of cognitive systems logic design. Post-Si debug: Familiarity with Post-Si debugs is preferable. Performance & Power Analysis: Familiarity with analysing Performance & Power Tools data and coming up with features solving PPA issues. India Infrastructure & Technology Hybrid Professional Bangalore, IN Bangalore (0063) IBM India Private Limited Architecture Design DevOps Engineering Linux Logic Design Power Tools Register-transfer Level Design Scripting Silicon Very High Speed Integrated Circuit Program Hardware Description Language Verilog Agile Central Processing Unit Instruction High Frequency Exception Handling Instruction Pipeline Accredited Residential Manager