Senior Manager - Systems Validation

Job Description :

The role will lead a technical validation team responsible for bring-up, validation, debug, and sign-off of FPGA silicon features and interfaces. This role requires strong hands-on silicon validation expertise, the ability to guide complex debug activities, and experience driving cross-functional execution across design, applications, systems, firmware, and global engineering teams.

The position involves creating and using validation designs partitioned across RTL and embedded processor applications, testing silicon on boards using lab equipment and protocol analyzers, reviewing specifications and validation plans, and ensuring issues are root-caused, tracked, resolved, and closed before sign-off.

Key Responsibilities :

• Lead FPGA silicon validation activities using Microchip FPGA design flows, validation methodologies, and lab-based debug practices.

• Manage and mentor a technical validation team across multiple projects, ensuring clear ownership, execution discipline, and timely delivery of milestones.

• Develop validation strategies, execution plans, test coverage goals, and sign-off criteria for block-level and subsystem-level features.

• Drive RTL-based and Embedded C-based test design development for feature validation, silicon bring-up, and system-level debug.

• Review specifications, validation plans, board schematics, and test requirements to ensure validation readiness and technical completeness.

• Lead board bring-up, feature validation, and debug of complex silicon functions using oscilloscopes, logic analyzers, protocol exercisers, protocol analyzers, and integrated logic analyzer tools.

• Perform root cause analysis for design, silicon, board, firmware, and system-level issues; validate workarounds and fixes through structured experiments.

• File, track, and drive closure of Bugzilla/Jira issues identified during design creation, validation, and sign-off phases.

• Provide clear status updates, risk assessments, dependency tracking, and action item follow-up in department reviews, project meetings, and stakeholder discussions.

• Collaborate with global teams, including teams in the US, for deep-dive debug discussions, technical reviews, issue resolution, and sign-off alignment.

• Document validation results, review findings with stakeholders, and secure formal sign-off for completed validation activities.

Requirements :

• BE/BTech or ME/MTech in Electronics, Electrical Engineering, Computer Engineering, or a related discipline with 13+ years of relevant industry experience.

• Proven experience managing or leading silicon validation teams, including planning, execution tracking, technical mentoring, and cross-functional coordination.

• Strong hands-on experience in FPGA silicon validation, board bring-up, lab debug, validation closure, and issue triage.

• Strong understanding of SERDES architecture, PMA features, equalization settings, eye capture, high-speed debug methods, and validation of data rates up to 100G.

• Hands-on validation experience in one or more protocols such as JESD204B, JESD204C, PCIe Gen4/Gen5, USB 3.2, 1588 PTP, MIPI, MACsec, or similar high-speed interfaces.

• Good knowledge of embedded processors and peripherals such as SPI, I3C, UART, NoC, Trace, and USB.

• Hands-on experience in C programming for embedded test applications, firmware-level debug, and validation automation.

• Strong capability to debug digital logic and analog behavior on PCBs using oscilloscopes, digital analyzers, protocol exercisers/analyzers, and integrated logic analyzers such as Synopsys Identify, Xilinx ChipScope, Altera SignalTap, or Lattice Reveal.

• Ability to handle complex use cases at block level and subsystem level, including test planning, failure isolation, workaround validation, and closure.

• Excellent written and verbal communication skills, with the ability to present technical status, risks, and recommendations clearly to engineering leaders and stakeholders.

• Strong commitment to quality, customer satisfaction, disciplined execution, and continuous improvement.

Travel Time : 0% - 25%