Senior ML Engineer

ABOUT THE ROLE

We're looking for an ML engineer who works across the full stack from model to silicon — comfortable optimizing training and inference performance on GPU/AI-accelerator infrastructure, building or tuning models, and adapting model and inference-engine design to the constraints of the underlying chip and its NPU. You'll move fluidly between algorithm work, systems-level software, and infrastructure work, closing the loop end-to-end rather than owning just one layer of the stack. This is a rare chance to work the full cycle of AI silicon, from model down to chip — something most ML engineers at large companies never get access to.

WHAT YOU'LL DO

• Optimize training and inference performance across GPU and AI-accelerator infrastructure, including MLOps pipelines

• Design, train, and evaluate ML models (deep learning, LLM, CV, or recommendation systems) and take them into production

• Work on at least one specialty area in depth — NPU hardening, systems-level software, inference engines, test/verification harnesses, or security-focused ML (see below)

• Build or optimize inference engines and serving runtimes against real hardware constraints — latency, memory, and power

• Collaborate closely with RTL/hardware, firmware, and QA teams to ship AI features end-to-end, from training through deployment and monitoring

WHAT WE'RE LOOKING FOR

• 3–5+ years of hands-on AI/ML experience; Bachelor's required, Master's preferred

• Hands-on experience with AI/ML infrastructure and performance — GPU clusters, distributed training, inference-serving optimization, MLOps pipelines

• Model / algorithm development experience — designing, training, and evaluating ML models

• Experience taking models into production — feature engineering, data pipelines, deployment

• AI chip / hardware-aware ML experience — optimizing inference engines for a specific chip, or adapting model architecture/quantization to chip constraints

• Hands-on experience in at least 1 of the following 5 specialty areas:

– NPU / AI-accelerator — hardening or extending an NPU core into production silicon, mapping models onto MAC/tensor-engine constraints, or NPU-aware RTL/DV work

– Systems / Sys-level software — BMC firmware, embedded Linux, RTOS (e.g. Zephyr), or other low-level system software

– Inference engine / runtime — built or materially optimized an inference engine or serving runtime against real hardware constraints

– Test / verification harness — built an automated harness that closes a loop, e.g. an agent-driven RTL/DV test runner or a hardware bring-up / MFG test harness