Senior or Staff Design Verification Engineer
Hands-on verification lead role at a well-funded semiconductor startup building chiplet power delivery technology for AI/advanced computing. Day to day: architect SystemVerilog/UVM verification environments for complex SoC/IP designs, run RTL and gate-level simulation (Xcelium/VCS), drive coverage closure, and mentor verification engineers. Hybrid: 3 days/week onsite in Vancouver, WA or Chandler,
- Compensation
- $160K–$190K / yr
- Location
- HQ - Vancouver, WA
- Work setup
- Hybrid
- Seniority
- Staff
- Employment
- Not specified
- Experience
- 10+ years
- Category
- Design
- Posted
Skills
Must have
- Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or related field
- 10+ years of experience in digital verification of SoCs with proven ownership of subsystems or full-chip verification
- Solid understanding of digital design fundamentals, FSMs, CDC, RDC, mixed-signal subsystems, and SoC integration
- Understanding of industry-standard protocols: AMBA, I2C, I3C, SPI, JTAG, and OBI
- Strong expertise in Verilog, SystemVerilog, UVM and class-based verification methodologies
- Strong expertise in constrained-random, coverage-driven verification, regression automation, and verification signoff
- Strong expertise in SystemVerilog Assertions (SVA) and formal verification techniques
- Strong expertise in Python, Perl, and UNIX/Linux shell scripting for automation
- Hands-on experience developing testbenches, drivers, monitors, scoreboards, assertions, and reusable verification IP
- Experience with industry-standard EDA tools (Synopsys, Cadence)
- Strong analytical and problem-solving skills; ability to debug complex issues, communicate clearly, mentor engineers, lead technical initiatives, and collaborate cross-functionally
Nice to have
- Working knowledge of PMIC architectures and power management principles
- Experience with formal verification techniques
Full description
Design Verification LeadReports To: Head of Engineering
About Us
Powerlattice is a well-funded semiconductor start-up company backed by leading Silicon Valley venture capital firms. We are developing groundbreaking chiplet power delivery technology that will transform how high-performance processors are powered, enabling the next generation of AI and advanced computing.
About the Role
We are seeking an experienced and hands-on Design Verification Lead to spearhead verification activities for complex SoC/IP designs, developing scalable SystemVerilog-based verification environments, verification strategies, reusable test infrastructure, and automated regression flows. This position drives functional verification from RTL through gate-level simulation, including coverage closure, assertions, timing verification, and debug. They will collaborate closely with RTL, analog, architecture, and silicon validation teams to identify and resolve design issues.
Key Responsibilities
- Lead verification planning and execution for complex digital and mixed-signal subsystems, including defining verification strategies, test scenarios, coverage goals, and signoff criteria.
- Architect, develop, and maintain SystemVerilog-based verification environments and reusable verification infrastructure.
- Develop directed, constrained-random, regression, and corner-case tests to verify functional requirements and design specifications.
- Develop reusable verification components and protocol-based test infrastructure for I2C/I3C, SPI, JTAG, AMBA, and OBI interfaces.
- Perform and support Clock Domain Crossing (CDC) verification for async and sync clock-domain interfaces.
- Develop and maintain UVM-based infrastructure and RAL models where applicable.
- Develop checkers, scoreboards, reference models, assertions, and functional coverage to provide comprehensive verification of design behavior.
- Perform RTL and gate-level simulation, including SDF-annotated GLS, to identify functional, timing, initialization, reset, and connectivity issues.
- Develop and optimize regression and GLS flows using Xcelium and VCS.
- Analyze functional and code coverage and drive coverage closure by identifying verification gaps and developing targeted tests.
- Debug complex RTL, testbench, simulation, and gate-level failures using waveform and log analysis.
- Work closely with RTL designers, analog designers, architects, and silicon validation teams to reproduce issues, determine root cause, and drive resolution.
- Review specifications and RTL to identify corner cases, interface issues, reset/clocking problems, and potential functional gaps.