Education: Master’s degree in Electrical Engineering (EE), Computer Science (CS), or a related field.
Experience: 4+ years of hands-on industry experience in block-level physical design and physical verification.
Technical Foundations: Deep understanding of VLSI design, digital integrated circuits, logic design, DFT, computer architecture, and design automation.
EDA Tool Expertise: Strong proficiency with industry-standard EDA tools and design flows (Synopsys, Cadence, or Siemens/Mentor Graphics).
Programming Skills: Solid scripting skills in TCL and Perl for design flow automation.
Work Location: Ability to work full-time at a customer site in the South Bay area on a hybrid schedule (3 days in-office, 2 days remote). No additional travel required.
Nice to have
Advanced Nodes: Hands-on experience with advanced process nodes; experience with TSMC N7/N5/N3/N2 is highly desirable.
Advanced Scripting: Highly skilled in developing custom TCL scripts to manipulate physical objects within P&R databases (e.g., Innovus or ICC2).
Integration Awareness: Strong understanding of chip-level integration constraints, low-power implementation methodologies (UPF/CPF), and interface requirements.
Ownership: Demonstrated ability to independently own and complete block-level Netlist-to-GDSII P&R and sign-off tasks.
Full description
Overview of Role
As a Senior Physical Design and Verification Engineer, you will focus on high-performance block-level design, verification, and physical sign-off. You will own the resolution of complex DRC, LVS, ERC, and Antenna violations, mitigate EMIR and Noise issues, and implement timing ECOs. While your day-to-day focus will be at the block level, you will maintain close alignment with full-chip integration requirements to ensure seamless top-level assembly.
In this role, you will work full-time on-site at a premier customer location in the South Bay (operating on a highly flexible 3-day in-office, 2-day remote hybrid schedule). You will join a dedicated team pushing the absolute limits of silicon technology, working directly on the world's most advanced A14 technology node.
Responsibilities
Block-Level Verification & Sign-off: Lead physical verification runs (DRC, LVS, ERC, Antenna) on complex blocks and resolve violations to achieve tape-out ready sign-off.
Power & Signal Integrity: Perform block-level Power IR/EM and Signal EM/Noise analysis, implementing robust fixes.
Floorplanning & Placement: Analyze block-level floorplans to resolve congestion, routability, and density issues.
Clock Tree Synthesis (CTS): Design and implement customized, high-performance clock tree structures within your blocks.
Timing Closure & ECOs: Implement functional and timing ECOs on high-performance blocks.
Block-Level P&R: Independently drive Netlist-to-GDSII Place and Route (P&R) tasks through to completion.
Flow Automation: Develop and utilize custom TCL/Perl scripts to automate design flows and manipulate physical objects within the P&R environment.
Minimum Qualifications
Education: Master’s degree in Electrical Engineering (EE), Computer Science (CS), or a related field.
Experience: 4+ years of hands-on industry experience in block-level physical design and physical verification.
Technical Foundations: Deep understanding of VLSI design, digital integrated circuits, logic design, DFT, computer architecture, and design automation.
EDA Tool Expertise: Strong proficiency with industry-standard EDA tools and design flows (Synopsys, Cadence, or Siemens/Mentor Graphics).
Programming Skills: Solid scripting skills in TCL and Perl for design flow automation.
Senior Physical Design Engineer(7051) at TSMC — aijobsearch
Work Location: Ability to work full-time at a customer site in the South Bay area on a hybrid schedule (3 days in-office, 2 days remote). No additional travel required.
Preferred Qualifications
Advanced Nodes: Hands-on experience with advanced process nodes; experience with TSMC N7/N5/N3/N2 is highly desirable.
Advanced Scripting: Highly skilled in developing custom TCL scripts to manipulate physical objects within P&R databases (e.g., Innovus or ICC2).
Integration Awareness: Strong understanding of chip-level integration constraints, low-power implementation methodologies (UPF/CPF), and interface requirements.
Ownership: Demonstrated ability to independently own and complete block-level Netlist-to-GDSII P&R and sign-off tasks.
Company Description
As a trusted technology and capacity provider, TSMC is driven by the desire to be:
The world’s leading dedicated semiconductor foundry
The technology leader with a strong reputation for manufacturing excellence
Advancing semiconductor manufacturing innovations to enable the future of technology
TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world. In North America, TSMC has a strong sales and service organization that works with customers by helping them achieve silicon success with cutting-edge technologies and manufacturing excellence. The Company has continued to accelerate its R&D investment and staffing in recent years and is expanding its manufacturing footprint to support customer innovation with 3D IC technologies and optimal manufacturing capacity.
Diversity statement
TSMC Technology, Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, or any other characteristic protected by applicable law.
TSMC is an equal opportunity employer prizing diversity and inclusion. We are committed to treating all employees and applicants for employment with respect and dignity. If you require reasonable accommodation due to a disability during the application or the recruiting process, please feel free to notify us at G_Accommodations@tsmc.com. TSMC confirms to all applicants its commitment to meet TSMC’s obligations under applicable employment law. Reasonable accommodations will be determined on a case-by-case basis.
For positions requiring access to technical data subject to export control regulations, including Export Administration Regulations, TSMC Technology, Inc. may have to obtain export licensing approval from the U.S. Government for certain individuals. All employment is contingent upon TSMC Technology, Inc. obtaining any export license or other approval that may be required by the U.S. Government.
Pay Transparency Statement
At TSMC, your base pay is only part of your overall total compensation package. At the time of this posting, this role typically pays a base salary between $120,000/yr and $160,000/yr. The range displayed reflects the minimum and maximum target for new hires. Actual pay may be more or less than the posted range. Factors that influence pay include the individual's skills, qualifications, education, experience and the position level and location.
TSMC’s total compensation package consists of market competitive pay, allowances, bonuses and comprehensive benefits. We also offer extensive development opportunities and programs.