Senior Silicon Design Verification Engineer, YouTube Video Accelerators

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a part of the Design Verification (DV) role in the Argos IP team, you will ensure the functional correctness of custom video codec ASICs for YouTube by managing a specialized High-Level Synthesis (HLS) workflow that requires verification at both the C/C++ and RTL levels. You will be responsible for bridging the gap between algorithmic intent and hardware implementation, employing a hybrid strategy that includes C++ software testing, C/RTL co-simulation, and traditional SystemVerilog/ Universal Verification Methodology (UVM) testbenches to guarantee equivalence and compliance. Your role demands comprehensive ownership of the verification life-cycle, from architectural planning and mixed-abstraction debugging to final coverage closure, while continuously refining methodologies to handle the specific complexities of HLS-based silicon design.

At YouTube, we believe that everyone deserves to have a voice, and that the world is a better place when we listen, share, and build community through our stories. We work together to give everyone the power to share their story, explore what they love, and connect with one another in the process. Working at the intersection of cutting-edge technology and boundless creativity, we move at the speed of culture with a shared goal to show people the world. We explore new ideas, solve real problems, and have fun — and we do it all together.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

• Lead comprehensive verification strategies and signoff for complex blocks where the source is C/C++, taking full ownership of quality from HLS code to generated RTL.

• Design and maintain advanced environments, including C/C++ GoogleTest for functional validation and SystemVerilog/UVM for RTL timing and system interactions.

• Employ HLS-specific methods such as C/RTL co-simulation, formal equivalence verification, and transaction-level modeling to ensure hardware fidelity.

• Drive complex bug hunting and coverage analysis across both C++ and RTL domains to ensure complete verification of the design transformation.

• Partner with design teams to optimize C++ code for verifiability and mentor junior engineers on the nuances of HLS verification.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.