Senior SoC Design Engineer - RTL/GDS

Job Description :

We are hiring an experienced Senior SoC Design Engineer / SoC Expert (RTL-to-GDSII) for a leading semiconductor client based in Bangalore.

We are seeking a highly experienced SoC Expert with 10+ years of experience in ASIC/SoC development and proven expertise across the complete RTL-to-GDSII design flow. The candidate will be responsible for leading the architecture, design, implementation, integration, verification, and physical realization of complex SoCs from specification through tape-out and silicon bring-up.

The ideal candidate should possess deep technical knowledge of digital design, SoC integration, synthesis, STA, low-power methodologies, DFT, physical design, and signoff flows while collaborating across cross-functional teams.

Key Responsibilities : SoC Architecture & Design :

• Define and review SoC architecture, micro-architecture, and design specifications.

• Drive RTL development using Verilog/SystemVerilog for NVM memory.

• Perform IP integration and top-level SoC assembly.

• Develop scalable and reusable design methodologies.

RTL Development & Verification :

• Lead RTL coding, lint, CDC, RDC, and quality checks.

• Collaborate with verification teams on test plans, coverage closure, and regression signoff.

• Debug functional issues and drive root-cause analysis.

• Ensure compliance with coding guidelines and design best practices.

Synthesis & Design Implementation :

• Own RTL-to-Gate synthesis flow and timing closure activities.

• Develop and maintain synthesis constraints (SDC).

• Drive area, power, and performance optimizations.

• Support ECO implementation and netlist signoff activities.

Physical Design & Signoff :

• Work closely with Physical Design teams through floorplanning, placement, CTS, routing, and optimization.

• Perform timing analysis and closure across multiple PVT corners.

• Support power integrity, IR drop, EM analysis, and low-power signoff.

• Analyze and resolve DRC, LVS, and physical verification issues.

• Drive GDSII release readiness and tape-out signoff.

DFT & Testability :

• Define and review DFT architecture including Scan, MBIST, LBIST, and JTAG.

• Support ATPG pattern generation and coverage closure.

• Collaborate with product engineering and validation teams during silicon bring-up.

Post-Silicon Support :

• Support first silicon debug and characterization.

• Analyze silicon failures and implement corrective actions.

• Work with system, validation, and customer teams to resolve issues.

Technical Leadership :

• Mentor junior engineers and provide technical guidance.

• Drive design reviews and signoff meetings.

• Contribute to methodology improvements and automation initiatives.

• Interface with customers, external partners, and executive stakeholders when required.

Required Qualifications :

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.

• 10+ years of experience in ASIC/SoC design and development.

• Proven experience in complete RTL-to-GDSII implementation flow.

Mandatory Skills :

• RTL-to-GDSII Flow

• Verilog/SystemVerilog

• SoC Integration

• Synthesis

• Static Timing Analysis (STA)

• Clock Domain Crossing (CDC)

• Low-Power Design Methodologies (UPF/CPF)

• Physical Design Concepts

• DFT (Scan, MBIST, LBIST, JTAG, ATPG)

• Silicon Debug & Bring-up