Senior SoC Verification/Validation Engineer
Senior engineer validates AI connectivity SoCs on emulation platforms, debugging high-speed interfaces like PCIe and Ethernet before silicon tape-out.
- Compensation
- $165K–$195K / yr
- Location
- San Jose, CA
- Work setup
- Not specified
- Seniority
- Senior
- Employment
- Not specified
- Experience
- 5+ years
- Category
- Industrial engineering
- Posted
Skills
Must have
- BS/MS in Electrical Engineering, Computer Engineering or related field.
- 5+ years of hands-on experience in pre-silicon verification/validation.
- Strong hands-on experience in running and debugging SOC simulation.
- Protocol knowledge in high-speed protocols such as PCIe, UALink and/or Ethernet is essential
- Proficiency in programming and scripting languages (System Verilog, C/C++, Python)
- Strong debugging and analytical skills
- Excellent communication skills and ability to work independently with minimal supervision.
- Currently based locally or open to relocation.
Nice to have
- Bring up and validation experience using the industry standard emulation platforms (Palladium or Zebu)
- Hands-on experience in running and debugging SOC simulation and emulation platforms.
Full description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at .
Job Description
We are looking for Senior SoC Verification/Validation Engineer who are passionate about bringing next-generation SoCs to life on industry-leading emulation platforms. You will play a critical role in validating complex SoCs for AI connectivity and cloud infrastructure, ensuring functionality and performance well before silicon tape-out.
Basic Responsibilities
- Play a key role in developing complex SOCs for AI connectivity and cloud infrastructures
- Bring up and validate high-speed serial interfaces such as PCIe, Ethernet and UALink, and overall SoC functionality
- Collaborate closely with Architecture, Design, Verification, and SW/FW teams to define and execute functional/performance validation plans
- Develop C/C++ FW and tests to validate and execute all test plan items
- Build tools and methodologies to validate and debug all HW and SW/FW issues on the emulation platform
Required Qualification
- BS/MS in Electrical Engineering, Computer Engineering or related field.
- 5+ years of hands-on experience in pre-silicon verification/validation.
- Strong hands-on experience in running and debugging SOC simulation.
- Protocol knowledge in high-speed protocols such as PCIe, UALink and/or Ethernet is essential
- Proficiency in programming and scripting languages (System Verilog, C/C++, Python)
- Strong debugging and analytical skills
- Excellent communication skills and ability to work independently with minimal supervision.
- Currently based locally or open to relocation.
Preferred Experience:
- Bring up and validation experience using the industry standard emulation platforms (Palladium or Zebu)
- Hands-on experience in running and debugging SOC simulation and emulation platforms.