SoC Design Implementation Engineer (Up to Principal Level)

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Company:

Qualcomm Vietnam Company Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

The SoC Design organization is seeking engineers to contribute to the implementation and front-end readiness of complex SoC, subsystem, and IP designs. This role focuses on design constraints, synthesis, timing analysis, power-intent implementation, and implementation collateral required to deliver high-quality netlists to downstream Physical Design, Design Verification, DFT, emulation, and signoff teams.

The successful candidate will work closely with RTL Design, SoC Architecture, Design Verification, Physical Design, DFT, CAD/methodology, power-management, and program teams across the global engineering organization.

The role requires a strong understanding of the transformation from RTL to synthesized netlist, including constraint development, synthesis optimization, timing and QoR analysis, low-power implementation using UPF, and resolution of design issues across RTL, constraints, libraries, tools, and flow configuration.

I. ResponsibilitiesDesign Implementation and Front-End Readiness

• Support implementation of complex SoC, subsystem, and IP designs from RTL through synthesis and handoff to downstream implementation teams.

• Review RTL hierarchy, design partitioning, clock and reset architecture, interface definitions, and implementation requirements.

• Prepare and maintain synthesis scripts, design configuration, file lists, libraries, operating conditions, scenarios, and implementation collateral.

• Coordinate design releases, dependencies, configuration updates, and implementation readiness across RTL, DV, DFT, PD, CAD, and architecture teams.

• Analyze design quality and identify RTL, constraint, library, or flow issues affecting timing, power, area, reliability, or implementation convergence.

• Support design reviews, implementation reviews, signoff reviews, and technical documentation activities.

• Investigate failures across RTL, synthesis, constraints, UPF, libraries, tool setup, and build environments; identify root cause and drive corrective action.

Constraint Development and Timing Readiness

• Develop, review, and maintain timing constraints for block, subsystem, and SoC-level designs.

• Create and validate clocks, generated clocks, clock relationships, clock uncertainty, input/output delays, loads, drive models, and operating scenarios.

• Define and review timing exceptions, including false paths, multicycle paths, asynchronous paths, clock groups, and case analysis.