SOC Frontend Integration Engineer
- Compensation
- Not disclosed
- Location
- Penang 15, Penang, Malaysia
- Work setup
- Not specified
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- Not specified
- Category
- Hardware
- Posted
Skills
Must have
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
- Experience with RTL design and integration using Verilog/SystemVerilog
- Knowledge various RTL quality checks required such as Lint, CDC/RDC, logical verification compile, emulation are required
- Solid understanding of SoC architectures and IP-based design methodologies
- Experience running and debugging frontend quality checks (lint, CDC, RDC)
- Comfortable working in a Linux environment and using scripting languages (Perl, Python, Tcl, or Shell)
- Strong debugging, problem-solving, and cross-functional communication skills
- Knowledge in AI/ML SoC to improve productivity in SoC Integration are advantageous
Full description
Job Details:
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Job Description:
We are looking for energetic & experienced SoC Frontend Integration Engineer at various level to be part of our growing team to drive the frontend integration of complex System-on-Chip (SoC) FPGA designs. In this role, you will own top-level SoC RTL integration and drive quality, scalability, and robustness across multiple IPs and subsystems.
You will work cross-functionally with architecture, IP design, verification, reliability, timing/power, physical design, and post-silicon teams, playing a critical role in taking SoCs from concept to tapeout.
Key Responsibilities
- Construct SoC frontend RTL integration, assembling internal and third-party IPs into top-level SoC designs
- Own SoC top-level RTL, hierarchy, connectivity, and scalability strategy
- Drive SoC-level frontend quality checks and closure
- Partner closely with verification teams to enable SoC-level simulation, emulation, and regression environments
- Collaborate closely with software team to enable integration of SoC into Quartus
- Provide high-quality frontend handoff to various SoC teams to enable other various checkouts like physical integration, timing/power convergence, pinout development, and reliability assessments.
- Debug and resolve complex integration issues across RTL, verification, and downstream flows
- Review IP deliverables and influence interfaces, clocking, reset, and power requirements
- Promote SoC integration best practices
- Continuously improve SoC integration flows, automation, and documentation
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Qualifications:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
- Experience with RTL design and integration using Verilog/SystemVerilog
- Knowledge various RTL quality checks required such as Lint, CDC/RDC, logical verification compile, emulation are required
- Solid understanding of SoC architectures and IP-based design methodologies
- Experience running and debugging frontend quality checks (lint, CDC, RDC)
- Comfortable working in a Linux environment and using scripting languages (Perl, Python, Tcl, or Shell)
- Strong debugging, problem-solving, and cross-functional communication skills
- Knowledge in AI/ML SoC to improve productivity in SoC Integration are advantageous
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Job Type:
Regular
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Shift:
Shift 1 (Malaysia)