SOC Platform Architect - IP Power
- Compensation
- Not disclosed
- Location
- San Diego, California, United States of America
- Work setup
- Onsite
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- 2+ years
- Category
- Architecture
- Posted
Skills
Must have
- Bachelor's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, or related work experience.
- Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to provid
- To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not aut
- EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender ide
- Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information
- Pay range and Other Compensation & Benefits:
- The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one compon
- If you would like more information about this role, please contact Qualcomm Careers.
Nice to have
- Exposure to Quality of Service, Clocks, Power management, Security and Debug architectures and their respective software interfaces
- Good knowledge in industry standard Interconnect Protocol and IO Devices Protocol
- Understanding of HW-SW interfaces and firmware
- Experience in post-silicon flows and debugs
Full description
##
Company:
Qualcomm Technologies, Inc.
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:GENERAL SUMMARY
The infrastructure IP Team consists of a multi-disciplinary group involved in the definition and design of Platform infrastructure HW components such as Interconnect (NOC), System Cache, Memory controllers and System MMU that are implemented in all Qualcomm SoCs. This position primarily involves working with HW designer to gather power estimation of SOC Infra HW IPs, analyze the data, identify architectural and micro-architectural bugs/limitations and propose fixes and/or optimizations for the same. The ideal candidate should have a strong background in ASIC design and computer architecture while demonstrating good system level design/architecture understanding. The candidate will be required to co-ordinate with domain leads to ensure a robust infrastructure deployment plan based on product requirements. It requires understanding of HW architecture, HW-&-SW feature trade-off, and the complete silicon HW end-2-end design flow.
Qualifications:
- Bachelor's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, or related work experience.
OR
- Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, architecture, or related work experience.
Skills/Experience
- Robust understanding of computer architecture
- Experience in system power architecture/design as well as exposure to power estimation flows.
- Basic understanding of end-end ASIC design flows
- Knowledge in SOC and Infrastructure IP (NOC, SMMU, Caches) HW architecture
- Exposure to some form of interconnect protocol
- Exposure to programming language for automation
- Ability to quickly react and adapt to changes
- Excellent communication skills
Preferred Qualification
- Exposure to Quality of Service, Clocks, Power management, Security and Debug architectures and their respective software interfaces
- Good knowledge in industry standard Interconnect Protocol and IO Devices Protocol
- Understanding of HW-SW interfaces and firmware
- Experience in post-silicon flows and debugs
Minimum Qualifications:
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.