Eridu AI
Software Engineer – High-Speed SerDes
Eridu AI is hiring a senior SerDes software engineer to lead bring-up, validation, and optimization of high-speed interfaces (224G PAM4 Ethernet, PCIe, UCIe chiplet interconnects) in advanced networking and compute silicon. Day to day, they'll write embedded C/C++ firmware and Python tooling for PHY initialization, link training, equalization, calibration, and diagnostics, working closely with ana
- Compensation
- Not disclosed
- Location
- Saratoga, CA
- Work setup
- Not specified
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- Not specified
- Category
- Software engineering
- Posted
Skills
Must have
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
- 10+ years of experience in SerDes firmware, PHY software, silicon bring-up, or high-speed interface validation
- Deep understanding of high-speed serial-link fundamentals (PAM4/NRZ signaling, channel loss, jitter/noise/crosstalk, CDR, FFE/CTLE/DFE, BER, eye diagrams, FEC)
- Hands-on experience bringing up and debugging at least one advanced SerDes generation, preferably 112G or 224G PAM4
- Strong experience with one or more of: Ethernet SerDes and IEEE 802.3 link training, PCIe Gen5/Gen6+ PHYs, or UCIe/high-speed die-to-die interfaces
- Strong embedded programming skills in C and C++
- Experience with Python or similar for automation, characterization, data analysis, and lab equipment control
- Experience programming SerDes registers via MDIO, I2C, SPI, PCIe config space, memory-mapped registers, or vendor-specific interfaces
- Familiarity with embedded processors, microcontrollers, real-time firmware, interrupts, DMA, and hardware/software interfaces
- Experience debugging pre-silicon models, emulation platforms, FPGA prototypes, and post-silicon devices
- Ability to interpret schematics, package/board topology, channel models, IBIS-AMI results, and signal-integrity reports
- Experience using lab equipment such as high-bandwidth oscilloscopes, BERTs, VNAs, protocol analyzers, and traffic generators
- Strong root-cause analysis skills spanning analog, digital, firmware, package, board, and system domains
Nice to have
- Experience with 224G-per-lane Ethernet PHYs and 800G, 1.6T, or higher-speed Ethernet systems
- Experience with PCIe 6.x or 7.0, including PAM4 signaling, FLIT mode, FEC, and lane margining
- Experience with UCIe PHY and adapter-layer bring-up in multi-die or chiplet-based systems
- Familiarity with long-reach, medium-reach, short-reach, very-short-reach, and die-to-die SerDes channels
- Experience integrating third-party SerDes IP into an ASIC or SoC
- Experience developing vendor-independent SerDes abstraction layers
- Knowledge of CMIS, pluggable optics, retimers, active electrical cables, and linear-drive optics
- Familiarity with IEEE 802.3, PCI-SIG, and UCIe Consortium specifications
- Experience with SerDes power optimization, fast link recovery, degradation detection, and field diagnostics
- Experience developing production screening, yield-analysis, and manufacturing-test solutions
- Experience with advanced process nodes, 2.5D packaging, interposers, and chiplet-based architectures
- Track record of technical leadership, cross-functional execution, and mentoring
Full description
Position Overview
We are seeking a highly experienced SerDes software engineer to lead the development, bring-up, validation, and optimization of next-generation high-speed interfaces. The successful candidate will work with 224 Gb/s-per-lane Ethernet SerDes, PCI Express, and UCIe chiplet interconnects in advanced networking and compute silicon.
This is a senior technical role requiring strong knowledge of SerDes architecture, PHY initialization, link training, equalization, calibration, diagnostics, and system-level signal-integrity behavior. The engineer will work closely with analog and mixed-signal designers, ASIC architects, firmware teams, validation engineers, board designers, and system software developers.
Key Responsibilities
- Develop embedded software and firmware for configuring, initializing, calibrating, and monitoring high-speed SerDes PHYs.
- Lead bring-up and optimization of 224G PAM4 SerDes used in Ethernet switch, networking, and accelerator products.
- Develop software support for PCIe SerDes, including link initialization, training, equalization, lane management, error recovery, and diagnostics.
- Develop software support for UCIe die-to-die interfaces, including PHY initialization, link training, lane repair, health monitoring, and failure analysis.
- Implement SerDes adaptation and calibration workflows, including:
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- Transmitter amplitude, pre-cursor, and post-cursor tuning
- Receiver CTLE, VGA, DFE, and CDR configuration
- Adaptive equalization
- Eye optimization and margining
- Lane-to-lane skew management
- Polarity inversion and lane remapping
- Background calibration and environmental compensation
- Develop APIs, drivers, firmware interfaces, command-line tools, and diagnostic utilities for SerDes control.
- Support Ethernet auto-negotiation and link training, including Clause 73 and Clause 72/136–related workflows where applicable.
- Support PCIe LTSSM interaction, preset and coefficient negotiation, lane margining, retraining, and recovery.
- Support UCIe link state management, PHY repair mechanisms, sideband interactions, and link reliability features.
- Create automated characterization and production-test software for:
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- PRBS generation and checking
- BER measurement
- Eye scans and bathtub curves
- Jitter and signal-margin analysis
- Loopback testing
- Lane failure isolation
- Channel and package characterization
- Analyze difficult link failures across silicon, package, board, connector, cable, and optical-module channels.