Software Engineer – High-Speed SerDes
Eridu, a Silicon Valley AI-infrastructure silicon startup, seeks a senior SerDes software engineer to develop embedded firmware and control software for 224G PAM4 Ethernet, PCIe, and UCIe SerDes PHYs — covering bring-up, link training, calibration, diagnostics, and automated characterization. Core stack: C/C++, Python, SerDes/PHY, lab instruments.
- Compensation
- $195K–$265K / yr
- Location
- Saratoga, United States
- Work setup
- Onsite
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- Not specified
- Category
- Software engineering
- Posted
Skills
Must have
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
- Typically 10+ years of experience in SerDes firmware, PHY software, silicon bring-up, or high-speed interface validation
- Deep understanding of high-speed serial-link fundamentals (PAM4/NRZ, channel/insertion/return loss, jitter, crosstalk, CDR, FFE, CTLE, DFE, BER, eye diagrams, FEC)
- Hands-on experience bringing up and debugging at least one advanced SerDes generation, preferably 112G or 224G PAM4
- Strong experience with Ethernet SerDes/IEEE 802.3 link training, PCIe Gen5/Gen6+ PHYs, and/or UCIe or another die-to-die interface
- Strong embedded programming skills in C and C++
- Experience with Python or similar for automation, characterization, data analysis, and lab equipment control
- Experience programming SerDes registers via MDIO, I²C, SPI, PCIe config space, memory-mapped registers, or vendor-specific interfaces
- Familiarity with embedded processors, microcontrollers, real-time firmware, interrupts, DMA, and hardware/software interfaces
- Experience debugging pre-silicon models, emulation platforms, FPGA prototypes, and post-silicon devices
- Ability to interpret schematics, package/board topology, channel models, IBIS-AMI results, and signal-integrity reports
- Experience using lab equipment such as high-bandwidth oscilloscopes, BERTs, VNAs, protocol analyzers, and traffic generators
- Strong root-cause analysis skills spanning analog, digital, firmware, package, board, and system domains
Nice to have
- Experience with 224G-per-lane Ethernet PHYs and 800G, 1.6T, or higher-speed Ethernet systems
- Experience with PCIe 6.x or 7.0 (PAM4 signaling, FLIT mode, FEC, lane margining)
- Experience with UCIe PHY and adapter-layer bring-up in multi-die or chiplet-based systems
- Familiarity with long-reach, medium-reach, short-reach, very-short-reach, and die-to-die SerDes channels
- Experience integrating third-party SerDes IP into an ASIC or SoC
- Experience developing vendor-independent SerDes abstraction layers
- Knowledge of CMIS, pluggable optics, retimers, active electrical cables, and linear-drive optics
- Familiarity with IEEE 802.3, PCI-SIG, and UCIe Consortium specifications
- Experience with SerDes power optimization, fast link recovery, degradation detection, and field diagnostics
- Experience developing production screening, yield-analysis, and manufacturing-test solutions
- Experience with advanced process nodes, 2.5D packaging, interposers, and chiplet-based architectures
- Track record of technical leadership, cross-functional execution, and mentoring
Full description
About Eridu
Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.
The company’s solutions and value proposition have been widely validated by leading hyperscalers.
Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.
Visit our website to learn more.
Position Overview
We are seeking a highly experienced SerDes software engineer to lead the development, bring-up, validation, and optimization of next-generation high-speed interfaces. The successful candidate will work with 224 Gb/s-per-lane Ethernet SerDes, PCI Express, and UCIe chiplet interconnects in advanced networking and compute silicon.
This is a senior technical role requiring strong knowledge of SerDes architecture, PHY initialization, link training, equalization, calibration, diagnostics, and system-level signal-integrity behavior. The engineer will work closely with analog and mixed-signal designers, ASIC architects, firmware teams, validation engineers, board designers, and system software developers.
Key Responsibilities
- Develop embedded software and firmware for configuring, initializing, calibrating, and monitoring high-speed SerDes PHYs.
- Lead bring-up and optimization of 224G PAM4 SerDes used in Ethernet switch, networking, and accelerator products.
- Develop software support for PCIe SerDes, including link initialization, training, equalization, lane management, error recovery, and diagnostics.
- Develop software support for UCIe die-to-die interfaces, including PHY initialization, link training, lane repair, health monitoring, and failure analysis.
- Implement SerDes adaptation and calibration workflows, including: