Sr Engineer - Physical Design
Senior Physical Design Engineer at SiFive (RISC-V semiconductor company) in Bengaluru, owning end-to-end RTL-to-GDS implementation — synthesis, floorplanning, place & route, and signoff — for next-gen compute IPs, co-optimizing with RTL/architecture teams to hit power, performance, and area targets using Synopsys and Cadence tools.
- Compensation
- Not disclosed
- Location
- Bengaluru, India
- Work setup
- Onsite
- Seniority
- Senior
- Employment
- Not specified
- Experience
- Not specified
- Category
- Design
- Posted
Skills
Must have
- 4+ years of hands-on physical design experience on advanced process nodes (7nm and below preferred)
- Solid experience with physical implementation of at least one major IP domain (CPUs, high-speed interconnects/fabrics, cache/memory hierarchies, or specialized accelerators)
- Understanding of the interplay between physical implementation and microarchitecture, with curiosity to adapt to different product architectures
- Strong proficiency with industry-standard EDA tools — Synopsys (Fusion Compiler, PrimeTime) and/or Cadence (Innovus, Tempus)
- Ability to debug complex physical design challenges (structural timing violations, routing congestion) with minimal supervision
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
- Right to work in India and authorization for access to export-controlled technology
Nice to have
- Contribute to flow/methodology/automation improvements and mentor junior engineers
Full description
About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description: About the Role
As a Senior Physical Design Engineer, you will be a core technical contributor responsible for the physical design implementation of our next-generation IPs. In this role, you will implement RTL2GDS ensuring the architecture and design achieve their peak physical potential.
We are looking for a "full-stack" physical design engineer who is deeply curious about the logic they are building. You should be the type of engineer who thrives at the convergence of microarchitecture and physical layout, enjoying the challenge of analyzing how an architectural datapath affects timing closure and how to push the boundaries of Power, Performance, and Area (PPA).
Key Responsibilities
- End-to-End Implementation: Own and execute the complete physical design flow (Synthesis, Floorplanning, P&R, Signoff) for major sub-systems and diverse IP blocks, ensuring they meet or exceed aggressive targets for PPA.
- Architectural & RTL Co-Optimization: Partner with RTL and Architecture teams from early-stage design to signoff. Identify physical and structural bottlenecks early—such as routing congestion in complex crossbars, dynamic power hot-spots in execution units, and interconnect span limits—and collaborate on microarchitectural or structural solutions to overcome them.
- Cross-Product PPA Execution: Apply advanced physical design techniques customized to the unique demands of different design classes. This includes implementing extreme leakage/dynamic power efficiency for edge IPs, rigorous reliability and redundancy structures for automotive standards, or maximizing bandwidth and throughput for high-speed fabrics.