Sr. Principal Analog Mixed-Signal Design Engineer

About SiTime

SiTime is the Precision Timing company.

Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com.

Job Summary

The Senior Principal Analog Mixed-Signal Design Engineer contributes to building precision timing circuits, leveraging SiTime’s industry-leading MEMS technology. These products have applications ranging from high-performance Networking and Communications Infrastructure to ultra-low power Mobile platforms, including wearable devices.

It is not necessary to meet all job requirements to be a qualified candidate for the position.

Responsibilities:

• Contribute to the architectural definition of the design and chip integration

• Technical leader for chip level design and verification simulations to ensure building blocks meet specifications at the schematic level and after post-layout extraction, while fully provisioning for DFT and DFM

• Work closely with Layout Engineers to validate proper layout, using all best-known methods

• Document assigned blocks, and hold preliminary and final design review meetings

• Actively participate in the chip bring-up, evaluation and characterization, with emphasis on owned blocks

• Work cross-functionally with Product, Characterization, Test, and Application Engineers on issues related to owned circuit blocks

• Coach, mentor and develop junior/mid-level analog designers, foster cross-functional collaboration.

Qualifications & Requirements:

• M.S. in Electrical Engineering or related field with minimum 15 years of related experience, or Ph.D. in Electrical Engineering with minimum 12 years of related experience

• Excellent academic record with published research projects prototyped and proven in silicon

• Detailed knowledge of CMOS circuits and noise analysis

• Core expertise in one of the following areas: