Sr. Staff ASIC Design Methodology Engineer, AI HW
Senior ASIC design methodology engineer advancing RTL development, verification, and physical implementation flows for Tenstorrent's Tensix AI compute cores — owning static analysis (Lint, CDC, RDC, DFT), logic equivalency, SDC/UPF development, and RTL-to-GDS enablement. Hybrid role based in Toronto, ON.
- Compensation
- $100K–$500K / yr
- Location
- Toronto, Ontario, Canada
- Work setup
- Not specified
- Seniority
- Staff
- Employment
- Not specified
- Experience
- Not specified
- Category
- Hardware
- Posted
Skills
Must have
- Deep expertise in ASIC design flows with a track record of leading methodology improvements
- Strong RTL design skills
- Expert in static and dynamic analysis tools for high-performance AI hardware
- Comfortable automating design checks and improving methodology for scalability and reuse across complex core configurations
- Effective collaboration across RTL, verification, and backend teams
Full description
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is seeking a Sr. Staff ASIC Design Methodology Engineer for our AI Hardware Tensix team. In this role, you will advance our design infrastructure and flows across RTL development, verification, and physical implementation specifically for our core AI compute engines. This role is ideal for senior engineers who thrive on improving design quality, enabling scalability, and automating methodologies that accelerate the silicon success of our next-generation Tensix cores.
This role is hybrid, based out of Toronto, ON.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- A strong advocate for design quality and productivity, with deep expertise in ASIC design flows and a track record of leading methodology improvements.
- Skilled in RTL design and an expert in static and dynamic analysis tools tailored for high-performance AI hardware.
- A technical leader comfortable automating design checks and improving methodology for scalability and reuse across complex Tensix core configurations.
- A collaborative engineer who partners effectively across RTL, verification, and backend teams to ensure seamless execution.
What We Need
- Develop and maintain ASIC design methodologies and infrastructure for RTL development and integration within the Tensix team.