Staff Engineer, PCIe Silicon Enablement

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

The Silicon Enablement Team drives first-silicon success by connecting architecture, design, verification, firmware, systems, and product teams throughout the silicon lifecycle. The team develops enablement plans, tests, firmware, and reusable infrastructure; brings up silicon and systems; investigates failures; and applies post-silicon learnings to improve products. Spanning IP, SoC, and SiP enablement, the work ranges from pre-silicon planning and tapeout through board and system bring-up, production firmware releases, and ongoing product support. This role combines firmware, automation, lab tools, and system-level debugging to solve complex problems and help shape the future of PCIe in AI/ML computing.

This role is hybrid and based in Santa Clara, California, Austin, Texas, Toronto, Canada or Vancouver, Canada.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You bring extensive PCIe experience across hardware, software, and systems, with a strong grasp of architecture and protocol behavior including link training and LTSSM, enumeration, configuration space, resets, and error recovery.

• You enjoy bringing hardware to life and solving complex problems across the hardware–software boundary, from pre-silicon planning and architecture alignment through first-silicon bring-up and product support.

• You are comfortable developing and debugging low-level firmware, automation, and reusable infrastructure for complex silicon systems, including PCIe controller and PHY bring-up.

• You are hands-on in the lab and can investigate clocks, sideband signals, SerDes/PHY behavior, lane issues, and system interactions using tools such as oscilloscopes, protocol analyzers, exercisers, JTAG, and trace tools.

• You understand how PCIe integrates with platform firmware and software, including UEFI/BIOS, operating-system drivers, DMA, interrupts, and IOMMUs and you are curious, collaborative, and effective in a fast-paced, output- and value-driven environment.