Sr. Staff Power Performance Architect
Senior Staff Power Performance Architect at d-Matrix owns pre-silicon power estimation for next-gen AI accelerators, spanning RTL-level and physical-design-level power analysis. They build an architectural power estimation tool for AI workloads and contribute to micro-architecture, RTL design, verification, and silicon bring-up using TCL, Python, and leading EDA tools.
- Compensation
- $165K–$265K / yr
- Location
- Santa Clara
- Work setup
- Hybrid
- Seniority
- Staff
- Employment
- Not specified
- Experience
- 8+ years
- Category
- Architecture
- Posted
Skills
Must have
- 8+ years of relevant experience in IC power/performance architecture, RTL, or physical design, with a Master's degree in Electrical Engineering, Computer Engineering, or Computer Science
- Solid understanding of power, performance, micro-architecture, RTL, and physical design in digital IC design, including the full IC design flow (Arch → uarch → RTL → Schematic → Layout → Verification
- Familiarity with at least one EDA tool for power estimation
- Ability to move fluidly between RTL, physical design, and automation, including building script utilities
- Programming proficiency in TCL and Python, with experience using libraries, APIs, data parsing, and algorithmic thinking
- Self-motivated with a fast, iterative approach to design work, sound engineering judgment, and a bias toward action
Nice to have
- Exposure to power estimation and performance metrics such as TDP, PMAX, EDP, Peak, and Average
- Familiarity with power/frequency scaling techniques (DFS, DVFS, AFS, AVFS)
- Familiarity with power delivery network (PDN) analysis, including resonance, impedance (Z(f)), and voltage droop analysis
Full description
Join d-Matrix and help build the future of AI inference. We’ve pioneered a memory-centric architecture that brings compute directly into memory, making AI faster, more energy efficient, and accessible on a global scale. From chips and software to rack-scale systems, our team is tackling some of AI infrastructure’s hardest challenges — and shipping breakthrough technology today. If you want to create what comes next and help make infinite inference possible, we’d love to hear from you.
Our culture is built on respect, collaboration, and direct communication. We value humility, we believe our different perspectives lead to better solutions, and we’re looking for people who are driven by execution and energized by hard problems.
Role Overview
d-Matrix is looking for a Senior Staff Power Performance Architect to own pre-silicon power estimation across our next-generation AI accelerators. In this role, you will drive both RTL-level and physical-design-level power estimation, and build an architectural power estimation tool that models power from system configuration and die-level metrics for AI workloads. You will partner closely with front-end architects, DV engineers, and backend design teams to identify power activity windows, define performance monitoring requirements, and translate that analysis into hardware capability improvements and die-level design changes. This role also contributes directly to micro-architecture and RTL design, verification, and silicon bring-up, making it central to how d-Matrix balances performance and power efficiency at the silicon level.
What You Will Do
- Own pre-silicon power estimation for design blocks, spanning both RTL-level and physical-design-level estimation.
- Partner with front-end and DV engineers to identify power activity windows, and work with the RTL team to implement estimation feedback and optimize power.
- Build an architectural power estimation tool for AI workloads that computes power from system configuration and die-level metrics, including workload profiling based on memory size, bandwidth, and gate counts of compute/memory blocks.
- Collaborate with frontend architects and backend design to define performance monitor availability, system requirements, and usage, then drive that analysis into hardware capability improvements and die-level design modifications.
- Lead micro-architecture and RTL design, synthesis, and logic/physical power-performance verification using leading-edge CAD tools and semiconductor process technologies.
- Design and implement performance-enabling and power-saving/monitoring functions that support efficient design, test, and debug, and participate in silicon bring-up and validation.
What You Will Bring
- 8+ years of relevant experience in IC power/performance architecture, RTL, or physical design, with a Master's degree in Electrical Engineering, Computer Engineering, or Computer Science.