Sr Staff Validation Engineer
- Compensation
- Not disclosed
- Location
- Santa Clara, CA
- Work setup
- Not specified
- Seniority
- Staff
- Employment
- Internship
- Experience
- 8+ years
- Category
- Industrial engineering
- Posted
Skills
Must have
- • Strong understanding of high-speed SERDES, equalization technique and PCIe protocols. • 8-10 years experience with High Speed IO testing, debugging and validation. • Strong lab skills with hands on
- Expected Base Pay Range (USD)
- The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role
- Additional Compensation and Benefit Elements
- All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran s
- Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
- Interview Integrity
- To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking
- These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in r
- This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be e
Full description
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As a Hardware and Silicon Validation Senior Staff Engineer at Marvell, you’ll be helping to deliver high bandwidth over long distances. This team performs analog validations on amplifiers that drive optical electronic devices and receivers. We also validate silicon photonics, do upper electronic measurements and support the coherent digital signal programming unit. This is a niche area at Marvell, working with cutting edge technologies used by many internal and external customers around the world.
What You Can Expect
- Complete responsibility of PCIe PHY Validation in post-silicon environment. Defining, documenting, executing, and reporting the overall PHY validation/test plan for Marvell storage devices.
- Lab-based silicon bring-up and unit test execution focused on PCIe Physical and PCS layer hardware and firmware functionality, while also extending to the protocol layer of the PCIe stack.
- Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER. Analyze and debug issues on Phy protocol of storage interface (SATA, SAS, PCIe, Ethernet).
- Troubleshoot failing tests with diagnostics, software tools, hardware analyzers, oscilloscopes, meters, logic/protocol analyzers. Leading collaborative technical discussions to drive resolution on technical issues.
- Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to PCIe PHY. Work closely with customers to address design issue and debug failure cases.
What We're Looking For
- Strong understanding of high-speed SERDES, equalization technique and PCIe protocols.
- 8-10 years experience with High Speed IO testing, debugging and validation.
- Strong lab skills with hands on experience, in system bring up, system testing and debug.
- In-depth working knowledge of test equipment used for SERDES characterization (Scope, BERT, Network analyzer, etc.).
- Strong analytical, problem-solving and communication skills.
Preferred/Plus:
- Working knowledge of PCIe interface and characterization. Working knowledge and experience on Ethernet and/or SAS/SATA SERDES is a definite plus.