Staff Analog Design Engineer, TX/RX Datapath
The Staff Analog Design Engineer will own the transistor-level design of high-speed SerDes transmit and receive datapath blocks for AI inference accelerators. This role involves the full design lifecycle from specification and simulation to silicon characterization using tools like Cadence Virtuoso, MATLAB, and Python.
- Compensation
- $155K–$250K / yr
- Location
- Santa Clara
- Work setup
- Hybrid
- Seniority
- Staff
- Employment
- Not specified
- Experience
- 8+ years
- Category
- Hardware
- Posted
Skills
Must have
- BS/MS/PhD in Electrical Engineering
- 8+ years of hands-on analog and mixed-signal circuit design experience
- Demonstrated ownership of a SerDes transmit or receive datapath block through to working silicon
- Deep knowledge of high-speed driver design, receive front-end design, and equalization
- Practical command of jitter and noise analysis
- Circuit design experience in advanced FinFET or GAA process nodes
- Hands-on use of industry-standard analog design and simulation tools (e.g., Cadence Virtuoso, Spectre)
- Experience with link/channel modeling (e.g., MATLAB, Python)
- Silicon bring-up and bench debug experience with high-speed lab equipment
Nice to have
- Die-to-die interconnect experience (UCIe, BoW, or proprietary D2D PHY)
- PAM4 signaling and DSP-based receiver architectures
- Familiarity with UCIe, OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/Gen7
- Experience porting a datapath block across process nodes
- IBIS-AMI model generation, or SerDes ATE and production test development
- Participation in or contribution to standards bodies
Full description
Join d-Matrix and help build the future of AI inference. We’ve pioneered a memory-centric architecture that brings compute directly into memory, making AI faster, more energy efficient, and accessible on a global scale. From chips and software to rack-scale systems, our team is tackling some of AI infrastructure’s hardest challenges — and shipping breakthrough technology today. If you want to create what comes next and help make infinite inference possible, we’d love to hear from you.
Our culture is built on respect, collaboration, and direct communication. We value humility, we believe our different perspectives lead to better solutions, and we’re looking for people who are driven by execution and energized by hard problems.
Role Overview
You will own the transmit and receive datapath of the high-speed SerDes on d-Matrix's IO chiplet — the interconnect that lets our inference accelerators scale beyond a single package. This is a hands-on, transistor-level design role on a small team, where you will personally carry blocks from specification through silicon characterization rather than handing specs off to someone else. The work spans porting proven datapath blocks to new process nodes and ground-up design of new blocks for our next-generation link, working closely with layout, package/signal-integrity, backend, and firmware engineers to bring your designs to working silicon.
What You Will Do
- Own transistor-level design of the SerDes transmit path: output drivers (SST and/or CML), pre-driver and serializer stages, and transmit-side FFE.
- Own transistor-level design of the receive front-end: termination and ESD-aware input network, CTLE, VGA, samplers, and where applicable ADC-based front-ends.
- Design and verify the equalization path — DFE and FFE architecture, tap resolution, and adaptation behavior — and own the trade study behind the architecture you choose.
- Derive block-level specifications from link budgets covering insertion loss, crosstalk, reflection, jitter, and BER targets, and defend those specifications in design review.
- Build the verification environment for your blocks — testbenches, PVT corner coverage, six-sigma Monte Carlo, transient noise, and post-layout back-annotated simulation — and provide behavioral and Verilog-A models for full-chip verification, supporting backend engineers through integration.
- Perform link and channel modeling in MATLAB, Python, or equivalent — S-parameter channel and package models, statistical eye and BER analysis, and equalization trade studies.
- Drive layout of your blocks in deep sub-micron nodes, working with layout engineers on floorplan, matching, shielding, current density, and parasitic control, and co-designing with package/signal-integrity engineers on bump maps, escape routing, and channel budgets.