Staff Design Verification Engineer

Renesas is looking for an experienced Staff Design Verification Engineer to join our team developing leading-edge memory interface products for data center, AI, and cloud computing applications. These products enable high-bandwidth, power-efficient memory solutions for intensive computing environments.

This role will contribute to the verification of advanced memory data buffer products, including DDR6 and future generations. The ideal candidate brings strong semiconductor design verification experience with SystemVerilog and UVM. Previous DDR or memory experience is an advantage, but is not required.

Key Responsibilities

• Drive verification activities for complex digital designs at the block and system level.
• Develop and execute verification plans based on functional and performance specifications.
• Develop, maintain, and optimize SystemVerilog/UVM verification environments and testbenches.
• Develop verification tests, functional coverage, checkers, and other verification components.
• Take ownership of verification environments and verification execution for assigned blocks and features.
• Drive and monitor coverage to ensure verification goals are achieved.
• Work closely with design engineers to ensure designs meet requirements and are effectively verifiable.
• Analyze verification results, debug failures, and identify functional or design issues.
• Develop efficient, reusable verification environments and methodologies with a focus on quality, performance, and ease of use.
• Identify and implement improvements to verification processes, methodologies, and design behavior.
• Participate in feasibility studies and technical reviews.
• Serve as a technical resource within the team, providing guidance on complex verification problems and sharing best practices.
• Communicate verification status, risks, and results to project stakeholders.

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent experience.
• 8+ years of related experience in semiconductor design verification.
• Strong experience in semiconductor design verification.
• Strong proficiency with SystemVerilog and hands-on experience using UVM (Universal Verification Methodology).
• Experience developing and debugging UVM-based verification environments and testbenches.
• Experience with verification planning, functional verification, coverage, checkers, test development, and debugging.
• Ability to independently own complex verification assignments and determine appropriate verification approaches.