Staff Hardware Engineer, Electrical Engineering Design, Google Cloud
Staff hardware engineer on Google's Platforms Infrastructure team who architects next-generation data center hardware end to end — board-level design, power delivery networks, and high-speed signal architecture — leading cross-functional teams from concept through high-volume manufacturing, with a focus on AI/ML platforms like GPUs and TPUs.
- Compensation
- $188K–$274K / yr
- Location
- Sunnyvale, CA, USA
- Work setup
- Not specified
- Seniority
- Staff
- Employment
- Not specified
- Experience
- 3+ years
- Category
- Hardware
- Posted
Skills
Must have
- Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, related field, or equivalent practical experience
- 6 years of experience working on electrical engineering design
- 3 years of experience in technical leadership
- Experience with Machine Learning (ML) and Artificial Intelligence (AI) hardware platforms, including GPUs and TPUs
Nice to have
- PhD in Electrical Engineering, Computer Engineering, Physics, related field, or equivalent practical experience
- 8 years of experience working on board design, system architecture, and electrical engineering design
- Experience with data center engineering, AI/ML, server, storage and networking products
- Experience solving system issues, driving technical innovation and technical roadmaps
- Ability to collect and organize details to reproduce results and explain findings
Full description
Our Platforms Infrastructure Engineering team designs and builds the
hardware and software technologies that power all of Google's services. Our computational challenges are complex and unique, enabled by cutting-edge custom hardware designed and made in-house. As a hardware engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will see those systems from concept all the way through to high-volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers, affecting millions of Google users.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $188000 - $274000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google.
- Drive end-to-end system architecture, technology roadmap, and board-level design for next-generation platforms, establishing technical direction and design standards across programs.
- Lead multi-disciplinary trade-off analyses across system, mechanical, thermal, and PCB layout teams to define high-density interconnect strategy, stackup architecture, and complex routing guidelines.
- Architect power delivery networks (PDN) and high-speed signal pathways in partnership with SI/PI experts, establishing guidelines that ensure performance at hyperscale.
- Oversee lab validation strategy, system bring-up, and root-cause analysis for critical architectural issues, mentoring engineering teams through complex debugging.
- Lead cross-functional engineering initiatives with Silicon, Firmware, Software, Thermal, Mechanical, and Operations teams to deliver cohesive, scalable infrastructure solutions. Influence manufacturing and vendor roadmaps to optimize Design for Manufacturing (DFM) and Design for Test (DFT) for high-volume, enterprise-grade deployments.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
- 6 years of experience working on electrical engineering design.
- 3 years of experience in technical leadership.
- Experience with Machine Learning (ML) and Artificial Intelligence (AI) Hardware platforms, including Graphics Processing Units (GPUs) and Tensor Processing Units (TPUs).
Preferred qualifications:
- PhD degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
- 8 years of experience working on board design, system architecture, and electrical engineering design.