Technical Program Manager
Hands-on digital design engineer (posted under a Technical Program Manager title) at a startup building novel, energy-efficient AI silicon. Day to day: defining micro-architecture, integrating third-party IP, writing RTL for timing-critical SoC blocks, and running synthesis, lint/CDC checks and verification support in Verilog with standard EDA tools.
- Compensation
- Not disclosed
- Location
- Mountain View, CA
- Work setup
- Not specified
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- 10+ years
- Category
- Project management
- Posted
Skills
Must have
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
- 8+ years of industry experience in digital ASIC/SoC design
- Expertise in Verilog RTL coding and digital design fundamentals
- Familiarity with standard EDA tools for simulation, synthesis, linting, and CDC analysis
- Understanding of the full ASIC design flow, from specification to tape-out
- Excellent written and verbal communication skills
- Ability to lead junior engineers and help develop their skills
Nice to have
- Experience creating digital designs: synchronous/asynchronous logic, state machines, bus protocols
- Experience developing scripts or tooling for design automation
- Experience optimizing designs for performance, power, or area
- Experience with modern design methods, including generative AI code development platforms
- Experience with analog mixed signal technology and interfaces
Full description
Technical Program Manager
Location: MTV
About Unconventional
We're a team of researchers and engineers, working across AI theory, silicon architecture, system modeling, agentic software, and AI systems. We tape out test chips every four months and release new models every six months. If that cadence sounds intense, it is. We're taking a big swing with big risk, and we need people who want to go deep on hard problems.
The Role
We're looking for a Technical Program Manager to own hardware-software co-development across our test chip program. You'll be the connective tissue between silicon, architecture, systems, and software teams—driving rapid prototyping cycles that let us validate new AI architectures quickly and learn fast.
This role leads to owning program execution for our first product.
Responsibilities
Drive test chip programs from architecture exploration through tapeout, bring-up, and characterization. You'll manage aggressive 4-month tapeout cycles, coordinating across silicon, hardware architecture, and systems teams.
Own hardware-software co-development schedules and dependencies. Our architecture is novel, which means software, compilers, and system integration are deeply intertwined with silicon decisions. You'll keep these workstreams synchronized.
Build and maintain the program infrastructure for rapid iteration—tracking experiments, capturing learnings, managing risk, and making tradeoffs visible so the team can move fast without losing coherence.
Work across AI theory, system modeling, and silicon teams to translate research directions into executable program plans. You'll need to understand what we're trying to learn from each test chip and structure the program around those goals.
Prepare the organization for product execution. As we move from prototyping toward our first product, you'll help evolve our program discipline from research velocity to production readiness.
What We're Looking ForMinimum qualifications
- 10+ years technical program management in silicon, systems, or ML infrastructure
- Strong written and verbal communication across highly technical teams
- BS/MS in Computer Science, Electrical Engineering, or related field
- Experience with hardware-software codesign programs—AI accelerators, novel compute architectures, or research silicon
Preferred qualifications
- Understanding of chip development lifecycle: architecture, RTL, tapeout, bring-up, validation
- Familiarity with compiler/runtime development and system software integration
- Fluency with agentic tools and AI-assisted workflows to scale program management without scaling headcount or meetings