Verification Platform Engineer, Platform Architecture
Engineer in Apple's Platform Architecture group improving pre-silicon verification of Apple silicon by building testbenches, verification infrastructure, and simulation/emulation platform R&D to boost DV simulation throughput. Core tech: SystemVerilog (UVM, DPI-C), EDA tooling, C++ software development, and Python/Perl scripting.
- Compensation
- Not disclosed
- Location
- Austin
- Work setup
- Not specified
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- Not specified
- Category
- Devops
- Posted
Skills
Must have
- Bachelor's degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent practical experience)
- Experience with SystemVerilog and EDA tooling
- Experience with software development (e.g., C++) and scripting (e.g., Perl or Python)
Nice to have
- Master's degree in Computer Engineering, Electrical Engineering, or another hardware-related field
- 3+ years of relevant experience
- Deep hands-on experience in Design Verification methodologies (UVM, DPI-C, testbench architecture)
- Experience applying LEC, linting / static analysis tools, waveform debugging, and simulation / emulation flows
- Strong understanding of SystemVerilog simulation semantics (events, time, glitches) and hardware representation (clocks, resets, latches)
- Strong communication skills with proven cross-functional collaboration across silicon engineering, DV, and EDA teams
- Experience with software optimization, HPC, co-simulation architectures, or hardware acceleration / emulation
- Development of agentic pipelines, graphs, skills, or similar work enabling AI productivity for other engineers
Full description
Apple’s Platform Architecture group develops the next generation of Apple hardware and the tools to make it possible. Our team builds high-performance verification systems that accelerate the development of Apple silicon. We aim to push the boundaries of pre-silicon validation with simulation solutions that apply and extend principles from hardware emulation.
This role bridges Apple's next-generation platform technology with DV methodology and tooling.
We are seeking an engineer with background in Design Verification who is interested in cutting-edge verification techniques and comfortable rapidly prototyping solutions. In this role, you will enable transformational improvements to simulation throughput for DV workflows through testbench design, infrastructure improvements, and platform R&D.
Minimum Qualifications
- Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent practical experience).
- Experience with SystemVerilog and EDA tooling.
- Experience with software development (e.g., using C++) and scripting (e.g., Perl or Python).
Preferred Qualifications
- Master’s degree in Computer Engineering, Electrical Engineering, or another hardware-related field.
- 3+ years of relevant experience.
- Deep hands-on experience in Design Verification methodologies (UVM, DPI-C, testbench architecture).
- Experience applying LEC, linting / static analysis tools, waveform debugging, and simulation / emulation flows.
- Strong understanding of SystemVerilog simulation semantics (events, time, glitches); intuitive grasp for hardware representation (clocks, resets, latches).
- Strong communication skills, with a proven history of cross-functional collaboration across silicon engineering, design verification, and EDA development teams and organizational boundaries.
- Experience with software optimization, high-performance computing (HPC), co-simulation architectures, or hardware acceleration / emulation.
- Development of agentic pipelines, graphs, skills, or similar work enabling AI productivity for other engineers.