Retym
VLSI Design Engineer
VLSI Design Engineer/Micro-architect responsible for designing cutting-edge communication systems from scratch using ASIC/FPGA with Verilog/SystemVerilog.
- Compensation
- Not disclosed
- Location
- Ramat Gan, Tel Aviv District
- Work setup
- Hybrid
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- 5+ years
- Category
- Hardware
- Posted
Skills
Must have
- 5 years of experience as ASIC/FPGA designer
- Strong Verilog/System-Verilog experience
- Familiar with simulation tools/environments, verification methodologies
- Strong team player, solid interpersonal skills
- Entrepreneurial can-do attitude, self-motivated, able to work independently
- BS/MS in EE/CE from lead universities
Nice to have
- Familiar with advanced design practices (Clock/Voltage domain crossing, Low Power Design, DFT)
- Design DSP oriented blocks
- Ethernet (100G and above)
- Scripting experience using several of the following: Python, Perl, TCL
Full description
We are looking for talented and experienced VLIS Design Engineers/Micro-architects.
As an VLIS Design Engineer/Micro-architect, you'll have the opportunity to design highly sophisticated, innovative new cutting edge communication systems from scratch.
In this position you will be responsible for coming up with creative solutions to architectural challenges and crafting the very fine details of the implementation
Requirements
Job requirements:
- 5 years of experience as ASIC/FPGA designer
- Strong Verilog/System-Verilog experience
- Familiar with simulation tools/environments, verification methodologies
- Strong team player, solid interpersonal skills
- Entrepreneurial can-do attitude, self-motivated, able to work independently
- BS/MS in EE/CE from lead universities
Background in one or more of the following domains is an advantage:
- Familiar with advanced design practices (Clock/Voltage domain crossing, Low Power Design, DFT)
- Design DSP of oriented blocks
- Ethernet (100G and above)
- Scripting experience using several of the following: Python, Perl, TCL